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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-12 15:25:30 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 10:17:29 -0800 |
| commit | 12d70ca8fbad73f2615e711e786f8b90fa005bee (patch) | |
| tree | 6459527e212b6e0ac65d99ad023606b6afd5e9f4 /techlibs/xilinx/synth_xilinx.cc | |
| parent | 46a89d7264f597be9ad10390fa44c22e16538548 (diff) | |
| download | yosys-12d70ca8fbad73f2615e711e786f8b90fa005bee.tar.gz yosys-12d70ca8fbad73f2615e711e786f8b90fa005bee.tar.bz2 yosys-12d70ca8fbad73f2615e711e786f8b90fa005bee.zip | |
xilinx: improve specify functionality
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 4011e09b0..bb3ced8da 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -619,8 +619,8 @@ struct SynthXilinxPass : public ScriptPass if (dff_mode) techmap_args += " -D DFF_MODE"; run("techmap " + techmap_args); - run("read_verilog -icells -specify -lib +/xilinx/abc9_model.v"); - std::string abc9_opts = " -box +/xilinx/abc9_xc7.box"; + run("read_verilog -icells -lib -specify +/xilinx/abc9_model.v"); + std::string abc9_opts; auto k = stringf("synth_xilinx.abc9.%s.W", family.c_str()); if (active_design->scratchpad.count(k)) abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str()); |