| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth_xilinx: Merge blackbox primitive libraries. | Marcin Kościelnicki | 2019-11-06 | 1 | -22/+3 |
| * | xilinx: Add URAM288 mapping for xcup | David Shah | 2019-10-23 | 1 | -1/+23 |
| * | xilinx: Add support for UltraScale[+] BRAM mapping | David Shah | 2019-10-23 | 1 | -1/+6 |
| * | xilinx: Support multiplier mapping for all families. | Marcin Kościelnicki | 2019-10-22 | 1 | -8/+45 |
| * | Call memory_dff before DSP mapping to reserve registers (fixes #1447) | N. Engelhardt | 2019-10-17 | 1 | -0/+1 |
| * | Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9 | Eddie Hung | 2019-10-08 | 1 | -7/+8 |
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| | * | Merge branch 'master' into eddie/abc_to_abc9 | Eddie Hung | 2019-10-04 | 1 | -3/+7 |
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| | * | | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 1 | -6/+7 |
| * | | | Add comment on why partial multipliers are 18x18 | Eddie Hung | 2019-10-04 | 1 | -4/+8 |
| * | | | Fix typo in check_label() | Eddie Hung | 2019-10-04 | 1 | -1/+1 |
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| * | | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9` | Eddie Hung | 2019-10-04 | 1 | -2/+6 |
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| * | Merge pull request #1359 from YosysHQ/xc7dsp | Eddie Hung | 2019-09-29 | 1 | -4/+32 |
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| | * | Re-order | Eddie Hung | 2019-09-27 | 1 | -1/+1 |
| | * | Typo | Eddie Hung | 2019-09-26 | 1 | -1/+1 |
| | * | select once | Eddie Hung | 2019-09-26 | 1 | -3/+5 |
| | * | Stop trying to be too smart by prematurely optimising | Eddie Hung | 2019-09-26 | 1 | -1/+3 |
| | * | Call 'wreduce' after mul2dsp to avoid unextend() | Eddie Hung | 2019-09-25 | 1 | -0/+1 |
| | * | Revert "Add a xilinx_finalise pass" | Eddie Hung | 2019-09-23 | 1 | -2/+0 |
| | * | Add a xilinx_finalise pass | Eddie Hung | 2019-09-23 | 1 | -0/+2 |
| | * | Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40 | Eddie Hung | 2019-09-20 | 1 | -1/+1 |
| | * | Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp | Eddie Hung | 2019-09-19 | 1 | -1/+3 |
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| | * | | synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2 | Eddie Hung | 2019-09-19 | 1 | -1/+4 |
| | * | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-18 | 1 | -6/+15 |
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| | * | | | Missing space | Eddie Hung | 2019-09-11 | 1 | -0/+1 |
| | * | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-11 | 1 | -10/+13 |
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| | * | | | | Move "(skip if -nodsp)" message to label | Eddie Hung | 2019-09-10 | 1 | -4/+4 |
| | * | | | | Really get rid of 'opt_expr -fine' by being explicit | Eddie Hung | 2019-09-10 | 1 | -3/+0 |
| | * | | | | Remove wreduce call | Eddie Hung | 2019-09-10 | 1 | -1/+0 |
| | * | | | | Add comment for why opt_expr is necessary | Eddie Hung | 2019-09-10 | 1 | -0/+2 |
| | * | | | | Revert "Remove "opt_expr -fine" call" | Eddie Hung | 2019-09-10 | 1 | -0/+1 |
| | * | | | | Rename label to map_dsp | Eddie Hung | 2019-09-10 | 1 | -1/+1 |
| | * | | | | Remove "opt_expr -fine" call | Eddie Hung | 2019-09-10 | 1 | -1/+0 |
| | * | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-05 | 1 | -9/+12 |
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| | * \ \ \ \ | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-30 | 1 | -14/+23 |
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| | * \ \ \ \ \ | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-08-30 | 1 | -1/+52 |
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| | | * \ \ \ \ \ | Merge branch 'master' into xc7dsp | David Shah | 2019-08-30 | 1 | -13/+68 |
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| | * | \ \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-20 | 1 | -14/+17 |
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| | * \ \ \ \ \ \ \ \ | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-08-15 | 1 | -1/+5 |
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| | | * | | | | | | | | xilinx: Rework labels for faster Verilator testing | David Shah | 2019-08-13 | 1 | -1/+5 |
| | * | | | | | | | | | Add DSP_A_MAXWIDTH_PARTIAL, refactor | Eddie Hung | 2019-08-13 | 1 | -1/+1 |
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| | * | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-12 | 1 | -1/+1 |
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| | * | | | | | | | | | Pack partial-product adder DSP48E1 packing | Eddie Hung | 2019-08-09 | 1 | -0/+2 |
| | * | | | | | | | | | Combine techmap calls | Eddie Hung | 2019-08-08 | 1 | -2/+1 |
| | * | | | | | | | | | Move xilinx_dsp to before alumacc | Eddie Hung | 2019-08-08 | 1 | -6/+4 |
| | * | | | | | | | | | Change $__softmul back to $mul | Eddie Hung | 2019-08-01 | 1 | -0/+1 |
| | * | | | | | | | | | Use single DSP_SIGNEDONLY macro | Eddie Hung | 2019-07-18 | 1 | -1/+1 |
| | * | | | | | | | | | Update comment | Eddie Hung | 2019-07-17 | 1 | -5/+3 |
| | * | | | | | | | | | Revert drop down to 24x16 multipliers for all | Eddie Hung | 2019-07-16 | 1 | -1/+1 |
| | * | | | | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-07-16 | 1 | -1/+5 |
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| | | * | | | | | | | | | xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 si... | David Shah | 2019-07-16 | 1 | -1/+5 |
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