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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-10 14:17:35 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-10 14:17:35 -0700 |
| commit | c460d10e60648c5126fe4a105ebf608b4f8d5e1a (patch) | |
| tree | f8865096c42cd848f671e5f167aca33261785fbd /techlibs/xilinx/synth_xilinx.cc | |
| parent | f3a55d3f06a21af06a267b3f9da8bd4df3d4aa82 (diff) | |
| download | yosys-c460d10e60648c5126fe4a105ebf608b4f8d5e1a.tar.gz yosys-c460d10e60648c5126fe4a105ebf608b4f8d5e1a.tar.bz2 yosys-c460d10e60648c5126fe4a105ebf608b4f8d5e1a.zip | |
Remove wreduce call
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index c99b77905..9ad28a933 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -328,7 +328,6 @@ struct SynthXilinxPass : public ScriptPass // Necessary for optimising away $shl cells, as well as $add cells // that have inputs with 1'b0 LSBs run("opt_expr -fine", " (skip if '-nodsp')"); - run("wreduce", " (skip if '-nodsp')"); run("xilinx_dsp", " (skip if '-nodsp')"); run("chtype -set $mul t:$__soft_mul"," (skip if '-nodsp')"); } |