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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 17:53:20 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 17:53:20 -0700 |
| commit | a5ac33f230b5dd20273f6636e5b573ef0478b8f9 (patch) | |
| tree | 6f67a20084e1490fec10824cf4ff9eb4c6fe14e8 /techlibs/xilinx/synth_xilinx.cc | |
| parent | aae2b9fd9c8dc915fadacc24962436dd7aedff36 (diff) | |
| parent | 0acc51c3d82f65f73fa9e475c6fc41beabd925a6 (diff) | |
| download | yosys-a5ac33f230b5dd20273f6636e5b573ef0478b8f9.tar.gz yosys-a5ac33f230b5dd20273f6636e5b573ef0478b8f9.tar.bz2 yosys-a5ac33f230b5dd20273f6636e5b573ef0478b8f9.zip | |
Merge branch 'master' into eddie/abc_to_abc9
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 5c2b1402c..beefcd451 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -475,13 +475,17 @@ struct SynthXilinxPass : public ScriptPass else if (abc9) { if (family != "xc7") log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, " - "will use timing for 'xc7' instead.\n", family.c_str()); + "will use timing for 'xc7' instead.\n", family.c_str()); run("techmap -map +/xilinx/abc9_map.v -max_iter 1"); run("read_verilog -icells -lib +/xilinx/abc9_model.v"); + std::string abc9_opts = " -box +/xilinx/abc9_xc7.box"; + abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY); + abc9_opts += " -nomfs"; if (nowidelut) - run("abc9 -lut +/xilinx/abc9_xc7_nowide.lut -box +/xilinx/abc9_xc7.box -W " + std::to_string(XC7_WIRE_DELAY)); + abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut"; else - run("abc9 -lut +/xilinx/abc9_xc7.lut -box +/xilinx/abc9_xc7.box -W " + std::to_string(XC7_WIRE_DELAY)); + abc9_opts += " -lut +/xilinx/abc9_xc7.lut"; + run("abc9" + abc9_opts); } else { if (nowidelut) |