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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-11 00:01:31 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-11 00:01:31 -0700 |
| commit | feb3fa65a3267acda76b7b6eea0e9ffedb281b85 (patch) | |
| tree | f635a53fa7e999dc6bdb9f05559baef445f2f2f4 /techlibs/xilinx/synth_xilinx.cc | |
| parent | b08797da6bf0061073dc662441e03b2fd218f11f (diff) | |
| parent | 486cbddd26a8db5bb2f2bbe3ea15e36b6c53a55e (diff) | |
| download | yosys-feb3fa65a3267acda76b7b6eea0e9ffedb281b85.tar.gz yosys-feb3fa65a3267acda76b7b6eea0e9ffedb281b85.tar.bz2 yosys-feb3fa65a3267acda76b7b6eea0e9ffedb281b85.zip | |
Merge remote-tracking branch 'origin/master' into xc7dsp
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 23 |
1 files changed, 13 insertions, 10 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 83be66daa..3d92c3e2c 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -273,6 +273,14 @@ struct SynthXilinxPass : public ScriptPass void script() YS_OVERRIDE { + std::string ff_map_file; + if (help_mode) + ff_map_file = "+/xilinx/xc6s_ff_map.v"; + else if (family == "xc6s") + ff_map_file = "+/xilinx/xc6s_ff_map.v"; + else + ff_map_file = "+/xilinx/xc7_ff_map.v"; + if (check_label("begin")) { if (vpr) run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v"); @@ -435,11 +443,9 @@ struct SynthXilinxPass : public ScriptPass } if (check_label("map_ffs")) { - if (abc9 || help_mode) { - run("techmap -map +/xilinx/ff_map.v", "('-abc9' only)"); - run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " - "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT", "('-abc9' only)"); - } + if (abc9 || help_mode) { + run("techmap -map " + ff_map_file, "('-abc9' only)"); + } } if (check_label("map_luts")) { @@ -472,15 +478,12 @@ struct SynthXilinxPass : public ScriptPass run("xilinx_srl -fixed -minlen 3", "(skip if '-nosrl')"); std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/cells_map.v"; if (help_mode) - techmap_args += " [-map +/xilinx/ff_map.v]"; + techmap_args += " [-map " + ff_map_file + "]"; else if (abc9) techmap_args += " -map +/xilinx/abc_unmap.v"; else - techmap_args += " -map +/xilinx/ff_map.v"; + techmap_args += " -map " + ff_map_file; run("techmap " + techmap_args); - if (!abc9 || help_mode) - run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " - "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT", "(without '-abc9' only)"); run("clean"); } |