| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-19 | 1 | -4/+12 | |
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| | * | | xilinx: Add xilinx_dffopt pass (#1557) | Marcin Kościelnicki | 2019-12-18 | 1 | -0/+1 | |
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| | * | | xilinx: Improve flip-flop handling. | Marcin Kościelnicki | 2019-12-18 | 1 | -4/+11 | |
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data. | |||||
| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-06 | 1 | -9/+8 | |
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| | * | xilinx: Add tristate buffer mapping. (#1528) | Marcin Kościelnicki | 2019-12-04 | 1 | -9/+8 | |
| | | | | | | | Fixes #1225. | |||||
| * | | Remove clkpart | Eddie Hung | 2019-12-05 | 1 | -4/+0 | |
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| * | | techmap abc_unmap.v before xilinx_srl -fixed | Eddie Hung | 2019-12-03 | 1 | -6/+5 | |
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| * | | clkpart -unpart into 'finalize' | Eddie Hung | 2019-11-28 | 1 | -3/+4 | |
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| * | | ean call after abc{,9} | Eddie Hung | 2019-11-27 | 1 | -1/+2 | |
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| * | | Move 'clean' from map_luts to finalize | Eddie Hung | 2019-11-26 | 1 | -1/+1 | |
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| * | | For abc9, run clkpart before ff_map and after abc9 | Eddie Hung | 2019-11-23 | 1 | -0/+2 | |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-19 | 1 | -30/+76 | |
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| | * | synth_xilinx: Merge blackbox primitive libraries. | Marcin Kościelnicki | 2019-11-06 | 1 | -22/+3 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First, there are no longer separate cell libraries for xc6s/xc7/xcu. Manually instantiating a primitive for a "wrong" family will result in yosys passing it straight through to the output, and it will be either upgraded or rejected by the P&R tool. Second, the blackbox library is expanded to cover many more families: everything from Spartan 3 up is included. Primitives for Virtex and Virtex 2 are listed in the Python file as well if we ever want to include them, but that would require having two different ISE versions (10.1 and 14.7) available when running cells_xtra.py, and so is probably more trouble than it's worth. Third, the blockram blackboxes are no longer in separate files — there is no practical reason to do so (from synthesis PoV, they are no different from any other cells_xtra blackbox), and they needlessly complicated the flow (among other things, merging them allows the user to use eg. Series 7 primitives and have them auto-upgraded to Ultrascale). Last, since xc5v logic synthesis appears to work reasonably well (the only major problem is lack of blockram inference support), xc5v is now an accepted setting for the -family option. | |||||
| | * | xilinx: Add URAM288 mapping for xcup | David Shah | 2019-10-23 | 1 | -1/+23 | |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | * | xilinx: Add support for UltraScale[+] BRAM mapping | David Shah | 2019-10-23 | 1 | -1/+6 | |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | * | xilinx: Support multiplier mapping for all families. | Marcin Kościelnicki | 2019-10-22 | 1 | -8/+45 | |
| | | | | | | | | | | | This supports several older families that are not yet supported for actual logic synthesis — the intention is to add them soon. | |||||
| | * | Call memory_dff before DSP mapping to reserve registers (fixes #1447) | N. Engelhardt | 2019-10-17 | 1 | -0/+1 | |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-10-08 | 1 | -5/+9 | |
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| | * | Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9 | Eddie Hung | 2019-10-08 | 1 | -7/+8 | |
| | |\ | | | | | | | Rename abc_* names/attributes to more precisely be abc9_* | |||||
| | | * | Merge branch 'master' into eddie/abc_to_abc9 | Eddie Hung | 2019-10-04 | 1 | -3/+7 | |
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| | * | | | Add comment on why partial multipliers are 18x18 | Eddie Hung | 2019-10-04 | 1 | -4/+8 | |
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| | * | | | Fix typo in check_label() | Eddie Hung | 2019-10-04 | 1 | -1/+1 | |
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| * | | | Remove -D_ABC9 | Eddie Hung | 2019-10-07 | 1 | -2/+0 | |
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| * | | | abc -> abc9 | Eddie Hung | 2019-10-04 | 1 | -3/+3 | |
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| * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-10-04 | 1 | -3/+7 | |
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| | * | | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9` | Eddie Hung | 2019-10-04 | 1 | -2/+6 | |
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| * | | | Use read_args for read_verilog | Eddie Hung | 2019-10-04 | 1 | -3/+6 | |
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| * | | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff | Eddie Hung | 2019-10-04 | 1 | -6/+7 | |
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| | * | | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 1 | -6/+7 | |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-29 | 1 | -4/+32 | |
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| | * | Merge pull request #1359 from YosysHQ/xc7dsp | Eddie Hung | 2019-09-29 | 1 | -4/+32 | |
| | |\ | | | | | | | DSP inference for Xilinx (improved for ice40, initial support for ecp5) | |||||
| | | * | Re-order | Eddie Hung | 2019-09-27 | 1 | -1/+1 | |
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| | | * | Typo | Eddie Hung | 2019-09-26 | 1 | -1/+1 | |
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| | | * | select once | Eddie Hung | 2019-09-26 | 1 | -3/+5 | |
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| | | * | Stop trying to be too smart by prematurely optimising | Eddie Hung | 2019-09-26 | 1 | -1/+3 | |
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| | | * | Call 'wreduce' after mul2dsp to avoid unextend() | Eddie Hung | 2019-09-25 | 1 | -0/+1 | |
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| | | * | Revert "Add a xilinx_finalise pass" | Eddie Hung | 2019-09-23 | 1 | -2/+0 | |
| | | | | | | | | | | | | | This reverts commit 23d90e0439ffef510632ce45a3d2aff1c129f405. | |||||
| | | * | Add a xilinx_finalise pass | Eddie Hung | 2019-09-23 | 1 | -0/+2 | |
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| | | * | Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40 | Eddie Hung | 2019-09-20 | 1 | -1/+1 | |
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| | | * | Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp | Eddie Hung | 2019-09-19 | 1 | -1/+3 | |
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| | | * | | synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2 | Eddie Hung | 2019-09-19 | 1 | -1/+4 | |
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| | | * | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-18 | 1 | -6/+15 | |
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| | | * | | | Missing space | Eddie Hung | 2019-09-11 | 1 | -0/+1 | |
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| | | * | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-11 | 1 | -10/+13 | |
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| | | * | | | | Move "(skip if -nodsp)" message to label | Eddie Hung | 2019-09-10 | 1 | -4/+4 | |
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| | | * | | | | Really get rid of 'opt_expr -fine' by being explicit | Eddie Hung | 2019-09-10 | 1 | -3/+0 | |
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| | | * | | | | Remove wreduce call | Eddie Hung | 2019-09-10 | 1 | -1/+0 | |
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| | | * | | | | Add comment for why opt_expr is necessary | Eddie Hung | 2019-09-10 | 1 | -0/+2 | |
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| | | * | | | | Revert "Remove "opt_expr -fine" call" | Eddie Hung | 2019-09-10 | 1 | -0/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit bfda921d0317bfb4cb6fc9de8a556c2258b709bc. | |||||
| | | * | | | | Rename label to map_dsp | Eddie Hung | 2019-09-10 | 1 | -1/+1 | |
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index : iCE40/yosys | |
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