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author | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 17:56:38 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 17:56:38 -0700 |
commit | a2ef93f03a1f75c25329c66d0e7d69da71e88e1f (patch) | |
tree | f4147c528dbb6cc4f181fb9eadfb6ef00dc73ca3 /techlibs/xilinx/synth_xilinx.cc | |
parent | f0cadb0de801391083f6cc91d842e8137396b820 (diff) | |
download | yosys-a2ef93f03a1f75c25329c66d0e7d69da71e88e1f.tar.gz yosys-a2ef93f03a1f75c25329c66d0e7d69da71e88e1f.tar.bz2 yosys-a2ef93f03a1f75c25329c66d0e7d69da71e88e1f.zip |
abc -> abc9
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
-rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 6c598acf2..07f3d9a8a 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -481,13 +481,13 @@ struct SynthXilinxPass : public ScriptPass "will use timing for 'xc7' instead.\n", family.c_str()); run("techmap -map +/xilinx/abc9_map.v -max_iter 1"); run("read_verilog -icells -lib +/xilinx/abc9_model.v"); - std::string abc9_opts = " -box +/xilinx/abc_xc7.box"; + std::string abc9_opts = " -box +/xilinx/abc9_xc7.box"; abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY); abc9_opts += " -nomfs"; if (nowidelut) - abc9_opts += " -lut +/xilinx/abc_xc7_nowide.lut"; + abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut"; else - abc9_opts += " -lut +/xilinx/abc_xc7.lut"; + abc9_opts += " -lut +/xilinx/abc9_xc7.lut"; run("abc9" + abc9_opts); } else { |