iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	synth_xilinx: techmap +/cmp2lut.v and +/cmp2lcu.v in 'coarse'	Eddie Hung	2020-04-03	1	-2/+1
*	Update xilinx for ABC9	Eddie Hung	2020-02-27	1	-1/+1
*	xilinx: improve specify functionality	Eddie Hung	2020-02-27	1	-2/+2
*	Auto-generate .box/.lut files from specify blocks	Eddie Hung	2020-02-27	1	-1/+1
*	abc9_ops: -prep_box, to be called once	Eddie Hung	2020-02-27	1	-1/+1
*	abc9_ops: -prep_lut and -write_lut to auto-generate LUT library	Eddie Hung	2020-02-27	1	-4/+2
*	Remove unnecessary comma	Eddie Hung	2020-02-07	1	-3/+2
*	xilinx: Add support for LUT RAM on LUT4-based devices.	Marcin Kościelnicki	2020-02-07	1	-2/+1
*	xilinx: Initial support for LUT4 devices.	Marcin Kościelnicki	2020-02-07	1	-16/+82
*	xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.	Marcin Kościelnicki	2020-02-07	1	-1/+8
*	xilinx: Add support for Spartan 3A DSP block RAMs.	Marcin Kościelnicki	2020-02-07	1	-1/+6
*	Add opt_lut_ins pass. (#1673)	Marcelina Kościelnicka	2020-02-03	1	-0/+1
*	synth_xilinx: cleanup help	Eddie Hung	2020-01-28	1	-6/+4
*	synth_xilinx: fix help when no active_design; fixes #1664	Eddie Hung	2020-01-28	1	-2/+3
*	Fix unresolved conflict from #1573	Eddie Hung	2020-01-28	1	-1/+1
*	Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate	N. Engelhardt	2020-01-28	1	-0/+3
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\| *	Duplicate tribuf call, credit to @mwkmwkmwk	Eddie Hung	2019-12-13	1	-1/+0
\| *	synth_xilinx: error out if tristate without '-iopad'	Eddie Hung	2019-12-12	1	-0/+4
* \|	Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623	Eddie Hung	2020-01-17	1	-2/+0
* \|	Merge pull request #1636 from YosysHQ/eddie/fix_synth_xilinx_W	Miodrag Milanović	2020-01-15	1	-1/+1
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\| * \|	synth_xilinx: fix default W value for non-xc7	Eddie Hung	2020-01-14	1	-1/+1
* \| \|	Merge pull request #1623 from YosysHQ/mmicko/edif_attr	Miodrag Milanović	2020-01-14	1	-1/+1
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\| * \|	Use CARRY4 for abc1 as well, preventing issues with Vivado	Miodrag Milanovic	2020-01-10	1	-1/+1
* \| \|	Another conflict	Eddie Hung	2020-01-11	1	-1/+0
* \| \|	synth_xilinx: synth_xilinx.abc9.xc7.W to replace XC7_WIRE_DELAY macro	Eddie Hung	2020-01-10	1	-4/+11
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* \|	synth_xilinx -dff to work with abc too	Eddie Hung	2020-01-02	1	-6/+14
* \|	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2020-01-02	1	-3/+3
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\| * \	Merge pull request #1601 from YosysHQ/eddie/synth_retime	Eddie Hung	2020-01-02	1	-3/+3
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\| \| * \|	Update doc that "-retime" calls abc with "-dff -D 1"	Eddie Hung	2019-12-30	1	-1/+1
\| \| * \|	Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""	Eddie Hung	2019-12-30	1	-2/+2
* \| \| \|	abc9 -keepff -> -dff; refactor dff operations	Eddie Hung	2020-01-02	1	-3/+3
* \| \| \|	Restore abc9 -keepff	Eddie Hung	2020-01-01	1	-1/+3
* \| \| \|	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-12-30	1	-12/+10
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\| * \| \|	Merge remote-tracking branch 'origin/master' into iopad_default	Miodrag Milanovic	2019-12-28	1	-1/+4
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\| \| * \|	xilinx_dsp: Initial DSP48A/DSP48A1 support.	Marcin Kościelnicki	2019-12-22	1	-1/+4
\| * \| \|	Addressed review comments	Miodrag Milanovic	2019-12-21	1	-2/+3
\| * \| \|	iopad no op for compatibility with old scripts	Miodrag Milanovic	2019-12-21	1	-0/+3
\| * \| \|	Make iopad option default for all xilinx flows	Miodrag Milanovic	2019-12-21	1	-14/+5
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\| * \|	Revert "Optimise write_xaiger"	Eddie Hung	2019-12-20	1	-5/+0
\| * \|	Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup	Eddie Hung	2019-12-19	1	-0/+5
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\| \| * \|	techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger	Eddie Hung	2019-12-06	1	-0/+5
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* \| \|	Add "synth_xilinx -dff" option, cleanup abc9	Eddie Hung	2019-12-30	1	-2/+14
* \| \|	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-12-19	1	-4/+12
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\| * \|	xilinx: Add xilinx_dffopt pass (#1557)	Marcin Kościelnicki	2019-12-18	1	-0/+1
\| * \|	xilinx: Improve flip-flop handling.	Marcin Kościelnicki	2019-12-18	1	-4/+11
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* \|	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-12-06	1	-9/+8
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\| *	xilinx: Add tristate buffer mapping. (#1528)	Marcin Kościelnicki	2019-12-04	1	-9/+8
* \|	Remove clkpart	Eddie Hung	2019-12-05	1	-4/+0
* \|	techmap abc_unmap.v before xilinx_srl -fixed	Eddie Hung	2019-12-03	1	-6/+5
* \|	clkpart -unpart into 'finalize'	Eddie Hung	2019-11-28	1	-3/+4