| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | move attributes to wires | Marcin Kościelnicki | 2019-08-13 | 1 | -155/+0 |
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| * | Add clock buffer insertion pass, improve iopadmap. | Marcin Kościelnicki | 2019-08-13 | 1 | -68/+76 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it. | ||||
| * | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-25 | 1 | -1/+1 |
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| | * | Add RAM32X1D support | Eddie Hung | 2019-06-24 | 1 | -2/+2 |
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| * | | Typo | Eddie Hung | 2019-05-28 | 1 | -1/+1 |
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| * | | Add whitebox support to DRAM | Eddie Hung | 2019-05-23 | 1 | -2/+2 |
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| * | Merge remote-tracking branch 'origin' into xc7srl | Eddie Hung | 2019-04-20 | 1 | -3/+3 |
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| | * | Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. | Keith Rothman | 2019-04-12 | 1 | -3/+3 |
| | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| * | | Remove duplicate STARTUPE2 | Eddie Hung | 2019-04-03 | 1 | -1/+0 |
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| * | | Merge remote-tracking branch 'origin/master' into xc7srl | Eddie Hung | 2019-03-22 | 1 | -5/+7 |
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| | * | xilinx: Add keep attribute where appropriate | David Shah | 2019-03-22 | 1 | -6/+7 |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | Merge remote-tracking branch 'origin/master' into xc7srl | Eddie Hung | 2019-03-14 | 1 | -2/+2 |
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| | * | Changes required for VPR place and route synth_xilinx. | Keith Rothman | 2019-03-01 | 1 | -2/+2 |
| | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| * | | Remove SRL16/32 from cells_xtra | Eddie Hung | 2019-02-28 | 1 | -2/+2 |
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| * | Add support for Xilinx PS7 block | Eddie Hung | 2018-11-10 | 1 | -0/+1 |
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| * | Add inout ports to cells_xtra.v | Clifford Wolf | 2018-10-04 | 1 | -2/+2 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Added black box modules for all the 7-series design elements (as listed in ↵ | Clifford Wolf | 2016-03-19 | 1 | -0/+145 |
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index : iCE40/yosys | |
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