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techlibs
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xilinx
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cells_xtra.sh
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Author
Age
Files
Lines
*
Merge remote-tracking branch 'origin/eddie/ram32x1d' into xc7mux
Eddie Hung
2019-06-24
1
-1
/
+1
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Add RAM32X1D support
Eddie Hung
2019-06-24
1
-2
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+2
*
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Typo
Eddie Hung
2019-05-28
1
-1
/
+1
*
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Add whitebox support to DRAM
Eddie Hung
2019-05-23
1
-2
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+2
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/
*
Merge remote-tracking branch 'origin' into xc7srl
Eddie Hung
2019-04-20
1
-3
/
+3
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\
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*
Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
Keith Rothman
2019-04-12
1
-3
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+3
*
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Remove duplicate STARTUPE2
Eddie Hung
2019-04-03
1
-1
/
+0
*
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Merge remote-tracking branch 'origin/master' into xc7srl
Eddie Hung
2019-03-22
1
-5
/
+7
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\
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*
xilinx: Add keep attribute where appropriate
David Shah
2019-03-22
1
-6
/
+7
*
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Merge remote-tracking branch 'origin/master' into xc7srl
Eddie Hung
2019-03-14
1
-2
/
+2
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*
Changes required for VPR place and route synth_xilinx.
Keith Rothman
2019-03-01
1
-2
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+2
*
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Remove SRL16/32 from cells_xtra
Eddie Hung
2019-02-28
1
-2
/
+2
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/
*
Add support for Xilinx PS7 block
Eddie Hung
2018-11-10
1
-0
/
+1
*
Add inout ports to cells_xtra.v
Clifford Wolf
2018-10-04
1
-2
/
+2
*
Added black box modules for all the 7-series design elements (as listed in ug...
Clifford Wolf
2016-03-19
1
-0
/
+145