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intel
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Author
Age
Files
Lines
*
intel: Use dfflegalize.
Marcelina Kościelnicka
2020-07-13
8
-178
/
+17
*
Update dff2dffe, dff2dffs, zinit to new FF types.
Marcelina Kościelnicka
2020-06-23
5
-5
/
+5
*
Use C++11 final/override keywords.
whitequark
2020-06-18
1
-4
/
+4
*
Add force_downto and force_upto wire attributes.
Marcelina Kościelnicka
2020-05-19
12
-0
/
+42
*
Get rid of dffsr2dff.
Marcelina Kościelnicka
2020-04-15
1
-1
/
+0
*
synth_intel_alm: alternative synthesis for Intel FPGAs
Dan Ravensloft
2020-04-15
1
-1
/
+0
*
Add log_experimental() and experimental() API and "yosys -x"
Claire Wolf
2020-01-27
1
-1
/
+1
*
Merge pull request #1604 from whitequark/unify-ram-naming
whitequark
2020-01-02
1
-5
/
+5
|
\
|
*
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
whitequark
2020-01-01
1
-5
/
+5
*
|
Update doc that "-retime" calls abc with "-dff -D 1"
Eddie Hung
2019-12-30
1
-1
/
+1
*
|
Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""
Eddie Hung
2019-12-30
1
-1
/
+1
|
/
*
synth_intel: a10gx -> arria10gx
Dan Ravensloft
2019-12-10
5
-4
/
+4
*
synth_intel: cyclone10 -> cyclone10lp
Dan Ravensloft
2019-12-10
5
-4
/
+4
*
techlibs/intel: Clean up Makefile
Ben Widawsky
2019-08-05
1
-15
/
+5
*
Merge branch 'ZirconiumX-synth_intel_m9k'
Clifford Wolf
2019-07-25
4
-5
/
+11
|
\
|
*
intel: Map M9K BRAM only on families that have it
Dan Ravensloft
2019-07-23
4
-5
/
+12
*
|
intel: Make -noiopads the default
Dan Ravensloft
2019-07-24
1
-8
/
+8
|
/
*
Merge pull request #1208 from ZirconiumX/intel_cleanups
David Shah
2019-07-18
1
-29
/
+14
|
\
|
*
synth_intel: Use stringf
Dan Ravensloft
2019-07-18
1
-7
/
+2
|
*
synth_intel: s/not family/no family/
Dan Ravensloft
2019-07-18
1
-2
/
+2
|
*
intel_synth: Fix help message
Ben Widawsky
2019-07-18
1
-1
/
+1
|
*
intel_synth: Small code cleanup to remove if ladder
Ben Widawsky
2019-07-18
1
-28
/
+10
|
*
intel_synth: Make family explicit and match
Ben Widawsky
2019-07-18
1
-2
/
+6
|
*
intel_synth: Minor code cleanups
Ben Widawsky
2019-07-18
1
-2
/
+6
*
|
synth_intel: rename for consistency with #1184
Dan Ravensloft
2019-07-18
1
-4
/
+4
|
/
*
synth_intel: Warn about untested Quartus backend
Dan Ravensloft
2019-07-07
1
-0
/
+3
*
Fix formatting for synth_intel.cc
Ben Widawsky
2019-05-09
1
-222
/
+211
*
Fixing issues in CycloneV cell sim
Diego
2019-04-11
1
-3
/
+9
*
Reduce amount of trailing whitespace in code base
Larry Doolittle
2019-02-28
2
-7
/
+7
*
Unify usage of noflatten among architectures
Miodrag Milanovic
2019-01-04
1
-2
/
+2
*
Fix typographical and grammatical errors and inconsistencies.
whitequark
2019-01-02
1
-1
/
+1
*
Changes in GoWin synth commands and ALU primitive support
Diego H
2018-12-03
1
-8
/
+8
*
Consistent use of 'override' for virtual methods in derived classes.
Henner Zeller
2018-07-20
1
-6
/
+6
*
Add "synth_intel --noiopads"
Clifford Wolf
2018-04-30
1
-2
/
+11
*
Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal val...
c60k28
2018-03-31
7
-60
/
+178
*
Add "dffinit -highlow" and fix synth_intel
Clifford Wolf
2018-01-09
1
-1
/
+1
*
Initial Cyclone 10 support
dh73
2017-11-08
5
-1
/
+308
*
Clean whitespace and permissions in techlibs/intel
Larry Doolittle
2017-10-05
21
-190
/
+190
*
Rename "write_verilog -nobasenradix" to "write_verilog -decimal"
Clifford Wolf
2017-10-03
1
-4
/
+1
*
Tested and working altsyncarm without init files
dh73
2017-10-01
2
-57
/
+59
*
Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ...
dh73
2017-10-01
21
-0
/
+2721