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| author | Dan Ravensloft <dan.ravensloft@gmail.com> | 2019-12-10 13:40:32 +0000 |
|---|---|---|
| committer | Dan Ravensloft <dan.ravensloft@gmail.com> | 2019-12-10 13:48:10 +0000 |
| commit | 85a14895ca31ec8c34bf5c296a5740a798b06693 (patch) | |
| tree | ca6e9e7d1166086c7085be3febba006ccdb1df78 /techlibs/intel | |
| parent | eab3272cdeed697bdb9664c2d8a133d336addb7c (diff) | |
| download | yosys-85a14895ca31ec8c34bf5c296a5740a798b06693.tar.gz yosys-85a14895ca31ec8c34bf5c296a5740a798b06693.tar.bz2 yosys-85a14895ca31ec8c34bf5c296a5740a798b06693.zip | |
synth_intel: a10gx -> arria10gx
Diffstat (limited to 'techlibs/intel')
| -rw-r--r-- | techlibs/intel/Makefile.inc | 2 | ||||
| -rw-r--r-- | techlibs/intel/arria10gx/cells_arith.v (renamed from techlibs/intel/a10gx/cells_arith.v) | 0 | ||||
| -rw-r--r-- | techlibs/intel/arria10gx/cells_map.v (renamed from techlibs/intel/a10gx/cells_map.v) | 0 | ||||
| -rw-r--r-- | techlibs/intel/arria10gx/cells_sim.v (renamed from techlibs/intel/a10gx/cells_sim.v) | 0 | ||||
| -rw-r--r-- | techlibs/intel/synth_intel.cc | 6 |
5 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/intel/Makefile.inc b/techlibs/intel/Makefile.inc index 92a83b5af..d97a9b58f 100644 --- a/techlibs/intel/Makefile.inc +++ b/techlibs/intel/Makefile.inc @@ -7,7 +7,7 @@ $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_m9k. $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_m9k.v)) # Add the cell models and mappings for the VQM backend -families := max10 a10gx cyclonev cyclone10lp cycloneiv cycloneive +families := max10 arria10gx cyclonev cyclone10lp cycloneiv cycloneive $(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_sim.v))) $(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_map.v))) #$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/arith_map.v)) diff --git a/techlibs/intel/a10gx/cells_arith.v b/techlibs/intel/arria10gx/cells_arith.v index 89fb4561f..89fb4561f 100644 --- a/techlibs/intel/a10gx/cells_arith.v +++ b/techlibs/intel/arria10gx/cells_arith.v diff --git a/techlibs/intel/a10gx/cells_map.v b/techlibs/intel/arria10gx/cells_map.v index 1430e8551..1430e8551 100644 --- a/techlibs/intel/a10gx/cells_map.v +++ b/techlibs/intel/arria10gx/cells_map.v diff --git a/techlibs/intel/a10gx/cells_sim.v b/techlibs/intel/arria10gx/cells_sim.v index e892b377e..e892b377e 100644 --- a/techlibs/intel/a10gx/cells_sim.v +++ b/techlibs/intel/arria10gx/cells_sim.v diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 5e6d2df2c..c8c690e45 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -36,7 +36,7 @@ struct SynthIntelPass : public ScriptPass { log("\n"); log("This command runs synthesis for Intel FPGAs.\n"); log("\n"); - log(" -family <max10 | a10gx | cyclone10lp | cyclonev | cycloneiv | cycloneive>\n"); + log(" -family <max10 | arria10gx | cyclone10lp | cyclonev | cycloneiv | cycloneive>\n"); log(" generate the synthesis netlist for the specified family.\n"); log(" MAX10 is the default target if no family argument specified.\n"); log(" For Cyclone IV GX devices, use cycloneiv argument; for Cyclone IV E, use cycloneive.\n"); @@ -148,7 +148,7 @@ struct SynthIntelPass : public ScriptPass { if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); if (family_opt != "max10" && - family_opt != "a10gx" && + family_opt != "arria10gx" && family_opt != "cyclonev" && family_opt != "cycloneiv" && family_opt != "cycloneive" && @@ -214,7 +214,7 @@ struct SynthIntelPass : public ScriptPass { } if (check_label("map_luts")) { - if (family_opt == "a10gx" || family_opt == "cyclonev") + if (family_opt == "arria10gx" || family_opt == "cyclonev") run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : "")); else run("abc -lut 4" + string(retime ? " -dff" : "")); |