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| author | Dan Ravensloft <dan.ravensloft@gmail.com> | 2019-11-19 10:19:00 +0000 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-04-15 11:40:41 +0200 |
| commit | 2e37e62e6b926ca1712b1636ef720748e382dc97 (patch) | |
| tree | 25936d690dff24f0cddcc5dbbfe68aea74500994 /techlibs/intel | |
| parent | 4c52691a58a469a525401bbc83c65f262b2a5504 (diff) | |
| download | yosys-2e37e62e6b926ca1712b1636ef720748e382dc97.tar.gz yosys-2e37e62e6b926ca1712b1636ef720748e382dc97.tar.bz2 yosys-2e37e62e6b926ca1712b1636ef720748e382dc97.zip | |
synth_intel_alm: alternative synthesis for Intel FPGAs
By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.
This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
Diffstat (limited to 'techlibs/intel')
| -rw-r--r-- | techlibs/intel/Makefile.inc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/techlibs/intel/Makefile.inc b/techlibs/intel/Makefile.inc index d97a9b58f..f751e341f 100644 --- a/techlibs/intel/Makefile.inc +++ b/techlibs/intel/Makefile.inc @@ -11,4 +11,3 @@ families := max10 arria10gx cyclonev cyclone10lp cycloneiv cycloneive $(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_sim.v))) $(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_map.v))) #$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/arith_map.v)) - |