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| author | Dan Ravensloft <dan.ravensloft@gmail.com> | 2019-07-18 18:41:34 +0100 |
|---|---|---|
| committer | Dan Ravensloft <dan.ravensloft@gmail.com> | 2019-07-18 19:02:23 +0100 |
| commit | 0c999ac2c4379273d560319d28591627de345a6a (patch) | |
| tree | a550aa1b2f381ebdb9133b26fe109ff5ae1a3682 /techlibs/intel | |
| parent | 50f5e29724bb6ea7f19279be7613ce693b7ea2da (diff) | |
| download | yosys-0c999ac2c4379273d560319d28591627de345a6a.tar.gz yosys-0c999ac2c4379273d560319d28591627de345a6a.tar.bz2 yosys-0c999ac2c4379273d560319d28591627de345a6a.zip | |
synth_intel: Use stringf
Diffstat (limited to 'techlibs/intel')
| -rw-r--r-- | techlibs/intel/synth_intel.cc | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 9a6df8c45..58ef25e17 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -166,11 +166,8 @@ struct SynthIntelPass : public ScriptPass { void script() YS_OVERRIDE { if (check_label("begin")) { - string cmd = "read_verilog -sv -lib +/intel/FAMILY/cells_sim.v"; - cmd.replace(cmd.find("FAMILY"), 6, family_opt); - if (check_label("family")) - run(cmd); + run(stringf("read_verilog -sv -lib +/intel/%s/cells_sim.v", family_opt.c_str())); // Misc and common cells run("read_verilog -sv -lib +/intel/common/m9k_bb.v"); @@ -220,9 +217,7 @@ struct SynthIntelPass : public ScriptPass { if (check_label("map_cells")) { if (!noiopads) run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(unless -noiopads)"); - string cmd = "techmap -map +/intel/FAMILY/cells_map.v"; - cmd.replace(cmd.find("FAMILY"), 6, family_opt); - run(cmd); + run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt.c_str())); run("dffinit -highlow -ff dffeas q power_up"); run("clean -purge"); |