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* Fix duplicated parameter name typoMiodrag Milanovic2020-11-181-1/+1
* synth_intel: Remove incomplete Arria 10 GX support.Marcelina Kościelnicka2020-08-215-192/+4
* intel: move Cyclone V support to intel_almDan Ravensloft2020-08-205-352/+8
* Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-071-2/+0
* intel: Use dfflegalize.Marcelina Kościelnicka2020-07-138-178/+17
* Update dff2dffe, dff2dffs, zinit to new FF types.Marcelina Kościelnicka2020-06-235-5/+5
* Use C++11 final/override keywords.whitequark2020-06-181-4/+4
* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-1912-0/+42
* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-151-1/+0
* synth_intel_alm: alternative synthesis for Intel FPGAsDan Ravensloft2020-04-151-1/+0
* Add log_experimental() and experimental() API and "yosys -x"Claire Wolf2020-01-271-1/+1
* Merge pull request #1604 from whitequark/unify-ram-namingwhitequark2020-01-021-5/+5
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| * Harmonize BRAM/LUTRAM descriptions across all of Yosys.whitequark2020-01-011-5/+5
* | Update doc that "-retime" calls abc with "-dff -D 1"Eddie Hung2019-12-301-1/+1
* | Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""Eddie Hung2019-12-301-1/+1
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* synth_intel: a10gx -> arria10gxDan Ravensloft2019-12-105-4/+4
* synth_intel: cyclone10 -> cyclone10lpDan Ravensloft2019-12-105-4/+4
* techlibs/intel: Clean up MakefileBen Widawsky2019-08-051-15/+5
* Merge branch 'ZirconiumX-synth_intel_m9k'Clifford Wolf2019-07-254-5/+11
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| * intel: Map M9K BRAM only on families that have itDan Ravensloft2019-07-234-5/+12
* | intel: Make -noiopads the defaultDan Ravensloft2019-07-241-8/+8
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* Merge pull request #1208 from ZirconiumX/intel_cleanupsDavid Shah2019-07-181-29/+14
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| * synth_intel: Use stringfDan Ravensloft2019-07-181-7/+2
| * synth_intel: s/not family/no family/Dan Ravensloft2019-07-181-2/+2
| * intel_synth: Fix help messageBen Widawsky2019-07-181-1/+1
| * intel_synth: Small code cleanup to remove if ladderBen Widawsky2019-07-181-28/+10
| * intel_synth: Make family explicit and matchBen Widawsky2019-07-181-2/+6
| * intel_synth: Minor code cleanupsBen Widawsky2019-07-181-2/+6
* | synth_intel: rename for consistency with #1184Dan Ravensloft2019-07-181-4/+4
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* synth_intel: Warn about untested Quartus backendDan Ravensloft2019-07-071-0/+3
* Fix formatting for synth_intel.ccBen Widawsky2019-05-091-222/+211
* Fixing issues in CycloneV cell simDiego2019-04-111-3/+9
* Reduce amount of trailing whitespace in code baseLarry Doolittle2019-02-282-7/+7
* Unify usage of noflatten among architecturesMiodrag Milanovic2019-01-041-2/+2
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-1/+1
* Changes in GoWin synth commands and ALU primitive supportDiego H2018-12-031-8/+8
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-6/+6
* Add "synth_intel --noiopads"Clifford Wolf2018-04-301-2/+11
* Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal val...c60k282018-03-317-60/+178
* Add "dffinit -highlow" and fix synth_intelClifford Wolf2018-01-091-1/+1
* Initial Cyclone 10 supportdh732017-11-085-1/+308
* Clean whitespace and permissions in techlibs/intelLarry Doolittle2017-10-0521-190/+190
* Rename "write_verilog -nobasenradix" to "write_verilog -decimal"Clifford Wolf2017-10-031-4/+1
* Tested and working altsyncarm without init filesdh732017-10-012-57/+59
* Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ...dh732017-10-0121-0/+2721
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