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* Add mul2dsp multiplier splitting rule and ECP5 mappingDavid Shah2019-07-082-0/+238
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Make doc consistentEddie Hung2019-06-141-1/+4
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* Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-123-2/+182
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| * Add "wreduce -keepdc", fixes #1016Clifford Wolf2019-05-201-2/+4
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-031-0/+2
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| | * Run "peepopt" in generic "synth" pass and "synth_ice40"Clifford Wolf2019-04-301-0/+2
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Improve $specrule interfaceClifford Wolf2019-04-231-2/+2
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Improve $specrule interfaceClifford Wolf2019-04-231-3/+4
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-231-0/+28
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std ↵Clifford Wolf2019-04-231-70/+70
| | | | | | | | | | | | | | | | | | nomenclature Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add $specify2 and $specify3 cells to simlibClifford Wolf2019-04-231-0/+147
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* / synth to take -abc9 argumentEddie Hung2019-02-201-5/+13
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* Merge pull request #772 from whitequark/synth_lutClifford Wolf2019-01-021-6/+40
|\ | | | | synth: add k-LUT mode
| * synth: add k-LUT mode.whitequark2019-01-021-2/+36
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| * synth: improve script documentation. NFC.whitequark2019-01-021-6/+6
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* | Merge pull request #771 from whitequark/techmap_cmp2lutClifford Wolf2019-01-022-1/+106
|\| | | | | cmp2lut: new techmap pass
| * cmp2lut: new techmap pass.whitequark2019-01-022-1/+106
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* | Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-022-2/+2
|/ | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.whitequark2018-12-052-0/+88
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* Fix typo.whitequark2018-12-051-2/+2
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* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-202-8/+8
| | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* Make -nordff the default in "prep"Clifford Wolf2018-05-301-9/+13
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "synth -noshare"Clifford Wolf2018-03-041-2/+11
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add $allconst and $allseq cell typesClifford Wolf2018-02-231-0/+24
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix minor typo in "prep" help messageClifford Wolf2017-12-191-1/+1
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* Add dff2ff.v techmap fileClifford Wolf2017-05-312-0/+15
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* Add $_ANDNOT_ and $_ORNOT_ gatesClifford Wolf2017-05-171-0/+38
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* Add $live and $fair cell types, add support for s_eventually keywordClifford Wolf2017-02-251-0/+16
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* Add $cover cell type and SVA cover() supportClifford Wolf2017-02-041-0/+8
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* Added $anyseq cell typeClifford Wolf2016-10-141-0/+12
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* Added $global_clock verilog syntax support for creating $ff cellsClifford Wolf2016-10-142-2/+23
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* Added $ff and $_FF_ cell typesClifford Wolf2016-10-122-1/+14
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* Added "prep -nokeepdc"Clifford Wolf2016-09-301-4/+12
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* Added "prep -nomem"Clifford Wolf2016-08-301-6/+16
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* Removed $aconst cell typeClifford Wolf2016-08-301-12/+0
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* Removed $predict againClifford Wolf2016-08-281-8/+0
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* Added "wreduce -memx"Clifford Wolf2016-08-201-2/+6
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* Added memory_memx pass, "memory -memx", and "prep -memx"Clifford Wolf2016-08-191-2/+17
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* Added $anyconst and $aconstClifford Wolf2016-07-271-0/+24
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* Added $initstate cell type and vlog functionClifford Wolf2016-07-211-0/+17
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* After reading the SV spec, using non-standard predict() instead of expect()Clifford Wolf2016-07-211-9/+1
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* Added basic support for $expect cellsClifford Wolf2016-07-131-0/+16
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* Added "prep -auto-top" and "synth -auto-top"Clifford Wolf2016-07-112-6/+23
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* Improved support for $sop cellsClifford Wolf2016-06-172-4/+4
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* Added $sop cell type and "abc -sop"Clifford Wolf2016-06-171-0/+28
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* Do not run "wreduce" in "prep -ifx"Clifford Wolf2016-06-081-2/+3
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* Added "proc_mux -ifx"Clifford Wolf2016-06-061-2/+11
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* Added "prep -flatten" and "synth -flatten"Clifford Wolf2016-04-242-7/+36
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* Converted "prep" to ScriptPassClifford Wolf2016-04-242-60/+47
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* Added "yosys -D" featureClifford Wolf2016-04-212-2/+2
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