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* Add docEddie Hung2019-06-211-3/+3
* Fix up ExclusiveDatabase with @cliffordwolf's helpEddie Hung2019-06-211-35/+34
* Merge branch 'master' into eddie/muxpackEddie Hung2019-06-218-11/+51
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| * Fix typo, fixes #1095Clifford Wolf2019-06-201-1/+1
| * Improve shregmap help message, fixes #1113Clifford Wolf2019-06-201-0/+2
| * Fix typoClifford Wolf2019-06-201-2/+2
| * Fixed the help summary line for a few commandsacw12512019-06-193-5/+5
| * Fix bug in #1078, add entry to CHANGELOGEddie Hung2019-06-191-3/+3
| * Use input default values in hierarchy passClifford Wolf2019-06-191-0/+38
* | Elaborate muxpack docEddie Hung2019-06-101-2/+6
* | Merge remote-tracking branch 'origin/master' into eddie/muxpackEddie Hung2019-06-101-12/+42
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| * Allow muxcover costs to be changedEddie Hung2019-06-071-12/+42
* | Comment O(N) -> O(N^2)Eddie Hung2019-06-071-1/+1
* | Extend ExclusiveDatabase to query SigSpec-s (for $pmux)Eddie Hung2019-06-071-19/+27
* | Add ExclusiveDatabase to check exclusive $eq/$logic_not cell resultsEddie Hung2019-06-071-1/+64
* | Resolve @cliffordwolf comment on redundant checkEddie Hung2019-06-071-10/+2
* | Resolve @cliffordwolf comment on sigmapEddie Hung2019-06-071-2/+2
* | Fix and test for balanced caseEddie Hung2019-06-061-10/+14
* | Support cascading $pmux.A with $mux.A and $mux.BEddie Hung2019-06-061-17/+25
* | More cleanupEddie Hung2019-06-061-15/+20
* | Fix spacingEddie Hung2019-06-061-6/+5
* | Non chain user check using next_sigEddie Hung2019-06-061-7/+5
* | Move muxpack from passes/techmap to passes/optEddie Hung2019-06-063-1/+1
* | Update docEddie Hung2019-06-061-4/+5
* | Add tests, fix for !=Eddie Hung2019-06-061-9/+32
* | Missing fileEddie Hung2019-06-061-0/+232
* | Initial adaptation of muxpack from shregmapEddie Hung2019-06-061-0/+1
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* Merge pull request #1071 from YosysHQ/eddie/fix_1070Clifford Wolf2019-06-061-2/+2
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| * Fix typo in opt_rmdffEddie Hung2019-06-051-2/+2
* | Merge pull request #1072 from YosysHQ/eddie/fix_1069Clifford Wolf2019-06-061-0/+5
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| * | Error out if no top module given before 'sim'Eddie Hung2019-06-051-0/+5
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* / Missing doc for -tech xilinx in shregmapEddie Hung2019-06-051-0/+3
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* Merge pull request #1067 from YosysHQ/clifford/fix1065Eddie Hung2019-06-051-1/+1
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| * Suppress driver-driver conflict warning for unknown cell types, fixes #1065Clifford Wolf2019-06-051-1/+1
* | Major rewrite of wire selection in setundef -initClifford Wolf2019-06-051-30/+89
* | Indent fixClifford Wolf2019-06-051-23/+25
* | Merge pull request #999 from jakobwenzel/setundefInitFixClifford Wolf2019-06-051-16/+23
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| * | initialize more registers in setundef -initJakob Wenzel2019-05-091-16/+23
* | | Fix typo in fmcombine log message, fixes #1063Clifford Wolf2019-06-051-2/+2
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* | Fix "tee" handling of log_streamsClifford Wolf2019-05-311-0/+5
* | Merge pull request #1049 from YosysHQ/clifford/fix1047Clifford Wolf2019-05-281-4/+11
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| * | Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047Clifford Wolf2019-05-281-4/+11
* | | Refactor hierarchy wand/wor handlingClifford Wolf2019-05-281-102/+143
* | | Merge branch 'master' into wandworStefan Biereigel2019-05-272-6/+71
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| * | Merge pull request #1026 from YosysHQ/clifford/fix1023Clifford Wolf2019-05-271-2/+3
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| | * | Keep zero-width wires in opt_clean if and only if they are ports, fixes #1023Clifford Wolf2019-05-221-2/+3
| * | | Revert enable checkEddie Hung2019-05-251-3/+1
| * | | opt_rmdff to optimise even in presence of enable signal, even removingEddie Hung2019-05-241-12/+29
| * | | Add commentsEddie Hung2019-05-241-1/+22
| * | | Resolve @cliffordwolf review, set even if !has_initEddie Hung2019-05-241-2/+1