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* Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improveEddie Hung2020-06-041-19/+60
|\ | | | | abc9: -dff improvements
| * abc9_ops: fix commentEddie Hung2020-05-301-1/+1
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| * abc9_ops: update messaging (credit to @Xiretza for spotting)Eddie Hung2020-05-301-4/+4
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| * abc9_ops: optimise to not derive unless attribute existsEddie Hung2020-05-291-4/+8
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| * abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_Eddie Hung2020-05-291-5/+22
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| * abc9_ops: -reintegrate to preserve flop namesEddie Hung2020-05-251-5/+25
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* | Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixesEddie Hung2020-06-031-2/+4
|\ \ | | | | | | abc9: fixes around handling combinatorial loops
| * | abc9_ops: -prep_xaiger exclude (* abc9_keep *) wires from toposortEddie Hung2020-05-251-2/+4
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* | techmap: remove dead variable. NFC.whitequark2020-06-031-1/+0
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* | techmap: use C++11 default member initializers. NFC.whitequark2020-06-021-16/+6
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* | techmap: simplify.whitequark2020-06-021-7/+1
| | | | | | | | `rewrite_filename` is already called in `Frontend::extra_args`.
* | techmap: use +/techmap.v instead of an ad-hoc code generator.whitequark2020-06-023-16/+1
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* | Merge pull request #1862 from boqwxp/cleanup_techmapclairexen2020-05-313-153/+158
|\ \ | | | | | | Clean up `passes/techmap/techmap.cc`
| * | techmap: Replace naughty `const_cast<>()`s.Alberto Gonzalez2020-05-141-2/+4
| | | | | | | | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * | techmap: Replace pseudo-private member usage with the range accessor ↵Alberto Gonzalez2020-05-141-3/+3
| | | | | | | | | | | | function and some naughty `const_cast<>()`s.
| * | techmap: sort celltypeMap as it determines techmap orderEddie Hung2020-05-141-1/+5
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| * | Replace `std::set`s using custom comparators with `pool`.Alberto Gonzalez2020-05-141-4/+4
| | | | | | | | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * | techmap: prefix special wires with backslash for use as IdStringEddie Hung2020-05-141-11/+12
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| * | Further clean up `passes/techmap/techmap.cc`.Alberto Gonzalez2020-05-141-5/+6
| | | | | | | | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * | Use `emplace()` for more efficient insertion into various `dict`s.Alberto Gonzalez2020-05-141-8/+8
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| * | Build constant bits directly rather than constructing an object and copying ↵Alberto Gonzalez2020-05-141-2/+5
| | | | | | | | | | | | its bits.
| * | Replace `std::set` with `pool` for `cell_to_inbit` and `outbit_to_cell`.Alberto Gonzalez2020-05-141-2/+2
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| * | Use `emplace()` rather than `insert()`.Alberto Gonzalez2020-05-141-1/+1
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| * | Clean up pseudo-private member usage and ensure range iteration uses ↵Alberto Gonzalez2020-05-141-17/+17
| | | | | | | | | | | | references where possible to avoid unnecessary copies.
| * | Clean up extraneous buffer.Alberto Gonzalez2020-05-141-5/+2
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| * | Replace `std::map` with `dict` for `unique_bit_id`.Alberto Gonzalez2020-05-141-1/+1
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| * | Replace `std::map` with `dict` for `port_new2old_map`, `port_connmap`, and ↵Alberto Gonzalez2020-05-141-3/+3
| | | | | | | | | | | | `cellbits_to_tplbits`.
| * | Replace `std::map` with `dict` for `connbits_map`, `cell_to_inbit`, and ↵Alberto Gonzalez2020-05-141-3/+3
| | | | | | | | | | | | `outbit_to_cell`.
| * | Replace `std::map` with `dict` for `TechmapWires` type.Alberto Gonzalez2020-05-141-1/+1
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| * | Replace `std::map` with `dict` for `celltypeMap`.Alberto Gonzalez2020-05-141-3/+3
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| * | Replace `std::set` with `pool` for `handled_cells` and `techmap_wire_names`.Alberto Gonzalez2020-05-141-4/+4
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| * | Replace `std::map` with `dict` for `positional_ports`.Alberto Gonzalez2020-05-141-1/+1
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| * | Add specialized `hash()` for type `dict` and use a `dict` instead of a ↵Alberto Gonzalez2020-05-141-4/+4
| | | | | | | | | | | | `std::map` for `techmap_cache` and `techmap_do_cache`.
| * | Replace `std::map` with `dict` for `simplemap_mappers`.Alberto Gonzalez2020-05-143-5/+5
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| * | Use `nullptr` instead of `NULL` in `passes/techmap/techmap.cc`.Alberto Gonzalez2020-05-141-10/+10
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| * | Replace `std::string` and `RTLIL::IdString` with `IdString` in ↵Alberto Gonzalez2020-05-141-21/+21
| | | | | | | | | | | | | | | | | | `passes/techmap/techmap.cc`. Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * | Do not modify design modules while iterating over `modules()`.Alberto Gonzalez2020-05-141-1/+4
| | | | | | | | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * | Clean up pseudo-private member usage, superfluous `std::vector` ↵Alberto Gonzalez2020-05-141-76/+70
| | | | | | | | | | | | instantiation, and `RTLIL::id2cstr()` usage in `passes/techmap/techmap.cc`.
* | | Merge pull request #2081 from YosysHQ/eddie/blackbox_astEddie Hung2020-05-301-25/+1
|\ \ \ | | | | | | | | blackbox: use Module::makeblackbox() method
| * | | blackbox: re-use existing Module::makeblackbox() methodEddie Hung2020-05-251-25/+1
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* | | Merge pull request #2018 from boqwxp/qbfsat-timeoutclairexen2020-05-301-13/+53
|\ \ \ | | | | | | | | smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, and CVC4.
| * | | smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, ↵Alberto Gonzalez2020-05-251-13/+53
| | | | | | | | | | | | | | | | and CVC4.
* | | | Merge pull request #1885 from Xiretza/mod-rem-cellsclairexen2020-05-297-15/+65
|\ \ \ \ | | | | | | | | | | Fix modulo/remainder semantics
| * | | | Add flooring division operatorXiretza2020-05-287-13/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor.
| * | | | Add flooring modulo operatorXiretza2020-05-287-12/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
* | | | | Merge pull request #2017 from boqwxp/qbfsat-cvc4clairexen2020-05-291-2/+6
|\ \ \ \ \ | | |/ / / | |/| | | qbfsat: Add support for CVC4.
| * | | | qbfsat: Add support for CVC4.Alberto Gonzalez2020-05-251-2/+6
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* | | | | Merge pull request #2016 from boqwxp/qbfsat-yicesclairexen2020-05-291-20/+47
|\| | | | | |/ / / |/| | | qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices the default.
| * | | qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices ↵Alberto Gonzalez2020-05-251-20/+47
| |/ / | | | | | | | | | | | | | | | the default. Ensures that "BV" is the logic whenever solving an exists-forall problem with Yices, moves the "(set-logic ...)" directive above any non-info line, sets the `ef-max-iters` parameter to a very high number when using Yices in exists-forall mode so as not to prematurely abandon difficult problems, and does not provide the incompatible "--incremental" Yices argument when in exists-forall mode.
* | | Merge pull request #2095 from rswarbrick/hier-typowhitequark2020-05-281-2/+2
|\ \ \ | | | | | | | | Fix small typos in documentation for hierarchy command
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