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author | Eddie Hung <eddie@fpgeh.com> | 2020-05-25 10:53:49 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-25 10:53:49 -0700 |
commit | 721283ac2a5724f72fd24a012c61e87e293f2b8a (patch) | |
tree | a9df977fdbbbba76c0fbaf90990dd11c177df974 /passes | |
parent | ae11156c90eec958cd9ab631a28c41eccc105e56 (diff) | |
download | yosys-721283ac2a5724f72fd24a012c61e87e293f2b8a.tar.gz yosys-721283ac2a5724f72fd24a012c61e87e293f2b8a.tar.bz2 yosys-721283ac2a5724f72fd24a012c61e87e293f2b8a.zip |
blackbox: re-use existing Module::makeblackbox() method
Diffstat (limited to 'passes')
-rw-r--r-- | passes/cmds/blackbox.cc | 26 |
1 files changed, 1 insertions, 25 deletions
diff --git a/passes/cmds/blackbox.cc b/passes/cmds/blackbox.cc index 5c0405f15..b8297cd77 100644 --- a/passes/cmds/blackbox.cc +++ b/passes/cmds/blackbox.cc @@ -48,31 +48,7 @@ struct BlackboxPass : public Pass { for (auto module : design->selected_whole_modules_warn()) { - pool<Cell*> remove_cells; - pool<Wire*> remove_wires; - - for (auto cell : module->cells()) - remove_cells.insert(cell); - - for (auto wire : module->wires()) - if (wire->port_id == 0) - remove_wires.insert(wire); - - for (auto it = module->memories.begin(); it != module->memories.end(); ++it) - delete it->second; - module->memories.clear(); - - for (auto it = module->processes.begin(); it != module->processes.end(); ++it) - delete it->second; - module->processes.clear(); - - module->new_connections(std::vector<RTLIL::SigSig>()); - - for (auto cell : remove_cells) - module->remove(cell); - - module->remove(remove_wires); - + module->makeblackbox(); module->set_bool_attribute(ID::blackbox); } } |