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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-30 09:01:03 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-30 09:01:03 -0700 |
| commit | 08d9703ecba375ba5588cbbb9dbf0f86757f6bb5 (patch) | |
| tree | 4337eff3bb30d51ae6e75780849822e0c311384b /passes | |
| parent | ea4374a2239e3975a7451b083e5756139596a02e (diff) | |
| download | yosys-08d9703ecba375ba5588cbbb9dbf0f86757f6bb5.tar.gz yosys-08d9703ecba375ba5588cbbb9dbf0f86757f6bb5.tar.bz2 yosys-08d9703ecba375ba5588cbbb9dbf0f86757f6bb5.zip | |
abc9_ops: fix comment
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index b4d4b77d5..2b79e1064 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -1439,7 +1439,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode) // treated as being "free"), in particular driving primary // outputs (real primary outputs, or cells treated as blackboxes) // or driving box inputs. - // Instead of just mapping those $_NOT_ gates into 2-input $lut-s + // Instead of just mapping those $_NOT_ gates into 1-input $lut-s // at an area and delay cost, see if it is possible to push // this $_NOT_ into the driving LUT, or into all sink LUTs. // When this is not possible, (i.e. this signal drives two primary |