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| author | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-04-20 04:46:09 +0000 |
|---|---|---|
| committer | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-05-14 20:06:54 +0000 |
| commit | f235f212ea242d765e38f4b317390657c1291f77 (patch) | |
| tree | 3c314b323744e3065d5062477820c9105eea2adb /passes | |
| parent | 62946218255eaea385fc62802c881bff256157fb (diff) | |
| download | yosys-f235f212ea242d765e38f4b317390657c1291f77.tar.gz yosys-f235f212ea242d765e38f4b317390657c1291f77.tar.bz2 yosys-f235f212ea242d765e38f4b317390657c1291f77.zip | |
Replace `std::set` with `pool` for `cell_to_inbit` and `outbit_to_cell`.
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/techmap.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 17d98847e..ab719cbaa 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -490,8 +490,8 @@ struct TechmapWorker } TopoSort<RTLIL::Cell*, IdString::compare_ptr_by_name<RTLIL::Cell>> cells; - dict<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit; - dict<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell; + dict<RTLIL::Cell*, pool<RTLIL::SigBit>> cell_to_inbit; + dict<RTLIL::SigBit, pool<RTLIL::Cell*>> outbit_to_cell; for (auto cell : module->selected_cells()) { |