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authorEddie Hung <eddie@fpgeh.com>2020-05-30 08:59:20 -0700
committerGitHub <noreply@github.com>2020-05-30 08:59:20 -0700
commitfe273faad11d67b1473b966e606ca982b91afd85 (patch)
treea9472d95d5e49a8ac7bde19b11edfcc0d70229be /passes
parentea46ed81f94547b1facf3b6e4b0866084ec3a072 (diff)
parent721283ac2a5724f72fd24a012c61e87e293f2b8a (diff)
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Merge pull request #2081 from YosysHQ/eddie/blackbox_ast
blackbox: use Module::makeblackbox() method
Diffstat (limited to 'passes')
-rw-r--r--passes/cmds/blackbox.cc26
1 files changed, 1 insertions, 25 deletions
diff --git a/passes/cmds/blackbox.cc b/passes/cmds/blackbox.cc
index 5c0405f15..b8297cd77 100644
--- a/passes/cmds/blackbox.cc
+++ b/passes/cmds/blackbox.cc
@@ -48,31 +48,7 @@ struct BlackboxPass : public Pass {
for (auto module : design->selected_whole_modules_warn())
{
- pool<Cell*> remove_cells;
- pool<Wire*> remove_wires;
-
- for (auto cell : module->cells())
- remove_cells.insert(cell);
-
- for (auto wire : module->wires())
- if (wire->port_id == 0)
- remove_wires.insert(wire);
-
- for (auto it = module->memories.begin(); it != module->memories.end(); ++it)
- delete it->second;
- module->memories.clear();
-
- for (auto it = module->processes.begin(); it != module->processes.end(); ++it)
- delete it->second;
- module->processes.clear();
-
- module->new_connections(std::vector<RTLIL::SigSig>());
-
- for (auto cell : remove_cells)
- module->remove(cell);
-
- module->remove(remove_wires);
-
+ module->makeblackbox();
module->set_bool_attribute(ID::blackbox);
}
}