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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-29 17:33:10 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-29 17:33:10 -0700 |
| commit | b17e8495b83bc8fa13a5ac982b44c0b68d71a68a (patch) | |
| tree | af831764050a1f98fef17237ddbbdea7898dd035 /passes | |
| parent | d3b53bc495a98dd9aa25c553e0f8237765d3ed7a (diff) | |
| download | yosys-b17e8495b83bc8fa13a5ac982b44c0b68d71a68a.tar.gz yosys-b17e8495b83bc8fa13a5ac982b44c0b68d71a68a.tar.bz2 yosys-b17e8495b83bc8fa13a5ac982b44c0b68d71a68a.zip | |
abc9_ops: optimise to not derive unless attribute exists
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 0b799c9f3..22da09e53 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -102,8 +102,6 @@ void check(RTLIL::Design *design, bool dff_mode) auto inst_module = design->module(cell->type); if (!inst_module) continue; - if (!inst_module->get_blackbox_attribute()) - continue; IdString derived_type; Module *derived_module; if (cell->parameters.empty()) { @@ -111,6 +109,10 @@ void check(RTLIL::Design *design, bool dff_mode) derived_module = inst_module; } else { + // Check potential (since its value may depend on a parameter, + // but not its existence) + if (!inst_module->has_attribute(ID::abc9_flop)) + continue; derived_type = inst_module->derive(design, cell->parameters); derived_module = design->module(derived_type); log_assert(derived_module); @@ -173,8 +175,6 @@ void prep_hier(RTLIL::Design *design, bool dff_mode) auto inst_module = design->module(cell->type); if (!inst_module) continue; - if (!inst_module->get_blackbox_attribute()) - continue; IdString derived_type; Module *derived_module; if (cell->parameters.empty()) { @@ -182,6 +182,10 @@ void prep_hier(RTLIL::Design *design, bool dff_mode) derived_module = inst_module; } else { + // Check potential for any one of those three + // (since its value may depend on a parameter, but not its existence) + if (!inst_module->has_attribute(ID::abc9_flop) && !inst_module->has_attribute(ID::abc9_box) && !inst_module->get_bool_attribute(ID::abc9_bypass)) + continue; derived_type = inst_module->derive(design, cell->parameters); derived_module = design->module(derived_type); } |