iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fix spacing	Eddie Hung	2019-06-21	1	-24/+24
*	Add doc	Eddie Hung	2019-06-21	1	-3/+3
*	Fix up ExclusiveDatabase with @cliffordwolf's help	Eddie Hung	2019-06-21	1	-35/+34
*	Merge branch 'master' into eddie/muxpack	Eddie Hung	2019-06-21	8	-11/+51
\|\
\| *	Fix typo, fixes #1095	Clifford Wolf	2019-06-20	1	-1/+1
\| *	Improve shregmap help message, fixes #1113	Clifford Wolf	2019-06-20	1	-0/+2
\| *	Fix typo	Clifford Wolf	2019-06-20	1	-2/+2
\| *	Fixed the help summary line for a few commands	acw1251	2019-06-19	3	-5/+5
\| *	Fix bug in #1078, add entry to CHANGELOG	Eddie Hung	2019-06-19	1	-3/+3
\| *	Use input default values in hierarchy pass	Clifford Wolf	2019-06-19	1	-0/+38
* \|	Elaborate muxpack doc	Eddie Hung	2019-06-10	1	-2/+6
* \|	Merge remote-tracking branch 'origin/master' into eddie/muxpack	Eddie Hung	2019-06-10	1	-12/+42
\|\\|
\| *	Allow muxcover costs to be changed	Eddie Hung	2019-06-07	1	-12/+42
* \|	Comment O(N) -> O(N^2)	Eddie Hung	2019-06-07	1	-1/+1
* \|	Extend ExclusiveDatabase to query SigSpec-s (for $pmux)	Eddie Hung	2019-06-07	1	-19/+27
* \|	Add ExclusiveDatabase to check exclusive $eq/$logic_not cell results	Eddie Hung	2019-06-07	1	-1/+64
* \|	Resolve @cliffordwolf comment on redundant check	Eddie Hung	2019-06-07	1	-10/+2
* \|	Resolve @cliffordwolf comment on sigmap	Eddie Hung	2019-06-07	1	-2/+2
* \|	Fix and test for balanced case	Eddie Hung	2019-06-06	1	-10/+14
* \|	Support cascading $pmux.A with $mux.A and $mux.B	Eddie Hung	2019-06-06	1	-17/+25
* \|	More cleanup	Eddie Hung	2019-06-06	1	-15/+20
* \|	Fix spacing	Eddie Hung	2019-06-06	1	-6/+5
* \|	Non chain user check using next_sig	Eddie Hung	2019-06-06	1	-7/+5
* \|	Move muxpack from passes/techmap to passes/opt	Eddie Hung	2019-06-06	3	-1/+1
* \|	Update doc	Eddie Hung	2019-06-06	1	-4/+5
* \|	Add tests, fix for !=	Eddie Hung	2019-06-06	1	-9/+32
* \|	Missing file	Eddie Hung	2019-06-06	1	-0/+232
* \|	Initial adaptation of muxpack from shregmap	Eddie Hung	2019-06-06	1	-0/+1
\|/
*	Merge pull request #1071 from YosysHQ/eddie/fix_1070	Clifford Wolf	2019-06-06	1	-2/+2
\|\
\| *	Fix typo in opt_rmdff	Eddie Hung	2019-06-05	1	-2/+2
* \|	Merge pull request #1072 from YosysHQ/eddie/fix_1069	Clifford Wolf	2019-06-06	1	-0/+5
\|\ \
\| * \|	Error out if no top module given before 'sim'	Eddie Hung	2019-06-05	1	-0/+5
\| \|/
* /	Missing doc for -tech xilinx in shregmap	Eddie Hung	2019-06-05	1	-0/+3
\|/
*	Merge pull request #1067 from YosysHQ/clifford/fix1065	Eddie Hung	2019-06-05	1	-1/+1
\|\
\| *	Suppress driver-driver conflict warning for unknown cell types, fixes #1065	Clifford Wolf	2019-06-05	1	-1/+1
* \|	Major rewrite of wire selection in setundef -init	Clifford Wolf	2019-06-05	1	-30/+89
* \|	Indent fix	Clifford Wolf	2019-06-05	1	-23/+25
* \|	Merge pull request #999 from jakobwenzel/setundefInitFix	Clifford Wolf	2019-06-05	1	-16/+23
\|\ \
\| * \|	initialize more registers in setundef -init	Jakob Wenzel	2019-05-09	1	-16/+23
* \| \|	Fix typo in fmcombine log message, fixes #1063	Clifford Wolf	2019-06-05	1	-2/+2
\| \|/ \|/\|
* \|	Fix "tee" handling of log_streams	Clifford Wolf	2019-05-31	1	-0/+5
* \|	Merge pull request #1049 from YosysHQ/clifford/fix1047	Clifford Wolf	2019-05-28	1	-4/+11
\|\ \
\| * \|	Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047	Clifford Wolf	2019-05-28	1	-4/+11
* \| \|	Refactor hierarchy wand/wor handling	Clifford Wolf	2019-05-28	1	-102/+143
* \| \|	Merge branch 'master' into wandwor	Stefan Biereigel	2019-05-27	2	-6/+71
\|\\| \|
\| * \|	Merge pull request #1026 from YosysHQ/clifford/fix1023	Clifford Wolf	2019-05-27	1	-2/+3
\| \|\ \
\| \| * \|	Keep zero-width wires in opt_clean if and only if they are ports, fixes #1023	Clifford Wolf	2019-05-22	1	-2/+3
\| * \| \|	Revert enable check	Eddie Hung	2019-05-25	1	-3/+1
\| * \| \|	opt_rmdff to optimise even in presence of enable signal, even removing	Eddie Hung	2019-05-24	1	-12/+29
\| * \| \|	Add comments	Eddie Hung	2019-05-24	1	-1/+22