iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero	Eddie Hung	2019-07-09	1	-0/+3
*	Update muxcover doc as per @ZirconiumX	Eddie Hung	2019-07-08	1	-5/+10
*	atoi -> stoi	Eddie Hung	2019-07-08	1	-5/+5
*	Add muxcover -mux2=cost option	Eddie Hung	2019-07-08	1	-1/+7
*	Make abc9 pass aware of optional ABCEXTERNAL override	Gabriel L. Somlo	2019-06-28	1	-0/+1
*	Fix spacing	Eddie Hung	2019-06-28	1	-2/+2
*	Do not use Module::remove() iterator version	Eddie Hung	2019-06-27	1	-5/+6
*	Remove &retime when abc9 -fast	Eddie Hung	2019-06-27	1	-1/+1
*	Cleanup abc9.cc	Eddie Hung	2019-06-27	1	-15/+17
*	Merge origin/master	Eddie Hung	2019-06-27	1	-6/+25
*	Fix spacing	Eddie Hung	2019-06-26	1	-38/+38
*	Support more than one port in the abc_scc_break attr	Eddie Hung	2019-06-26	1	-38/+42
*	nullptr check	Eddie Hung	2019-06-25	1	-0/+1
*	Fix for abc_scc_break is bus	Eddie Hung	2019-06-24	1	-21/+23
*	More meaningful error message	Eddie Hung	2019-06-24	1	-0/+2
*	Do not use log_id as it strips \\, also fix scc for \|wire\| > 1	Eddie Hung	2019-06-24	1	-13/+30
*	Fix abc9's scc breaker, also break on abc_scc_break attr	Eddie Hung	2019-06-24	1	-9/+31
*	Merge remote-tracking branch 'origin/master' into xaig	Eddie Hung	2019-06-21	2	-48/+114
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\| *	Merge pull request #1108 from YosysHQ/clifford/fix1091	Eddie Hung	2019-06-21	1	-45/+99
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\| \| *	Replace "muxcover -freedecode" with "muxcover -dmux=cost"	Clifford Wolf	2019-06-21	1	-15/+14
\| \| *	Add "muxcover -freedecode"	Clifford Wolf	2019-06-21	1	-0/+14
\| \| *	Improvements in muxcover	Clifford Wolf	2019-06-20	1	-38/+55
\| \| *	Add support for partial matches to muxcover, fixes #1091	Clifford Wolf	2019-06-20	1	-7/+31
\| * \|	Merge pull request #1085 from YosysHQ/eddie/shregmap_improve	Eddie Hung	2019-06-21	1	-3/+15
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\| \| *	Actually, there might not be any harm in updating sigmap...	Eddie Hung	2019-06-20	1	-3/+1
\| \| *	Add comment as per @cliffordwolf	Eddie Hung	2019-06-20	1	-0/+11
\| \| *	Revert "Try way that doesn't involve creating a new wire"	Eddie Hung	2019-06-11	1	-15/+10
* \| \|	Do not rename non LUT cells in abc9	Eddie Hung	2019-06-21	1	-11/+16
* \| \|	Fix gcc warning of potentially uninitialised	Eddie Hung	2019-06-20	1	-2/+2
* \| \|	Fix simple_abc9/generate test with 1'bx at MSB	Eddie Hung	2019-06-20	1	-1/+1
* \| \|	Merge remote-tracking branch 'origin/master' into xaig	Eddie Hung	2019-06-20	2	-3/+5
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\| * \|	Improve shregmap help message, fixes #1113	Clifford Wolf	2019-06-20	1	-0/+2
\| * \|	Fix bug in #1078, add entry to CHANGELOG	Eddie Hung	2019-06-19	1	-3/+3
* \| \|	Do not call "setundef -zero" in abc9	Eddie Hung	2019-06-20	1	-5/+2
* \| \|	&scorr before &sweep, remove &retime as recommended	Eddie Hung	2019-06-17	1	-1/+1
* \| \|	Copy not move parameters/attributes	Eddie Hung	2019-06-17	1	-3/+4
* \| \|	Fix leak removing cells during ABC integration; also preserve attr	Eddie Hung	2019-06-17	1	-25/+26
* \| \|	Re-enable &dc2	Eddie Hung	2019-06-17	1	-1/+1
* \| \|	Cleanup	Eddie Hung	2019-06-16	1	-51/+7
* \| \|	Get rid of compiler warnings	Eddie Hung	2019-06-14	1	-5/+5
* \| \|	Update abc9 -D doc	Eddie Hung	2019-06-14	1	-1/+2
* \| \|	Enable "abc9 -D <num>" for timing-driven synthesis	Eddie Hung	2019-06-14	1	-9/+9
* \| \|	Further cleanup based on @daveshah1	Eddie Hung	2019-06-14	1	-10/+0
* \| \|	Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig	Eddie Hung	2019-06-14	1	-0/+9
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\| * \| \|	ecp5: Add abc9 option	David Shah	2019-06-14	1	-0/+9
* \| \| \|	Remove extra semicolon	Eddie Hung	2019-06-14	1	-1/+1
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* \| \|	Rip out all non FPGA stuff from abc9	Eddie Hung	2019-06-12	1	-343/+111
* \| \|	Fix spelling	Eddie Hung	2019-06-12	1	-1/+1
* \| \|	Be more precise when connecting during ABC9 re-integration	Eddie Hung	2019-06-12	1	-1/+3
* \| \|	Remove hacky wideports_split from abc9	Eddie Hung	2019-06-12	1	-52/+4