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author | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 16:52:09 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 16:52:09 -0700 |
commit | f81a189fb893c62cf6e6f020608ca23db211e31f (patch) | |
tree | 21c19dfd6ea04cee05ba8485a7c133a00fe2b841 /passes/techmap | |
parent | 90dc4d82de2eb7193caef797203d0e4cc8d32d3e (diff) | |
download | yosys-f81a189fb893c62cf6e6f020608ca23db211e31f.tar.gz yosys-f81a189fb893c62cf6e6f020608ca23db211e31f.tar.bz2 yosys-f81a189fb893c62cf6e6f020608ca23db211e31f.zip |
Fix spelling
Diffstat (limited to 'passes/techmap')
-rw-r--r-- | passes/techmap/abc.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 5b19d84fb..15e79f9d1 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1453,7 +1453,7 @@ struct AbcPass : public Pass { log("internally. This is not going to \"run ABC on your design\". It will instead run\n"); log("ABC on logic snippets extracted from your design. You will not get any useful\n"); log("output when passing an ABC script that writes a file. Instead write your full\n"); - log("design as BLIF file with write_blif and the load that into ABC externally if\n"); + log("design as BLIF file with write_blif and then load that into ABC externally if\n"); log("you want to use ABC to convert your design into another format.\n"); log("\n"); log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n"); |