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| author | Clifford Wolf <clifford@clifford.at> | 2019-06-20 15:23:55 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-06-20 15:23:55 +0200 |
| commit | 06eb87bcb795b44dc0c9e42c0b2a495c05d23881 (patch) | |
| tree | a39f2224ab899b96f509a5ee9f914f443bacefe9 /passes/techmap | |
| parent | a8c85d1b4b810e2ea31770e37e1414b7f1a15283 (diff) | |
| download | yosys-06eb87bcb795b44dc0c9e42c0b2a495c05d23881.tar.gz yosys-06eb87bcb795b44dc0c9e42c0b2a495c05d23881.tar.bz2 yosys-06eb87bcb795b44dc0c9e42c0b2a495c05d23881.zip | |
Improve shregmap help message, fixes #1113
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/shregmap.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 21dfe9619..18e60fa6b 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -605,9 +605,11 @@ struct ShregmapPass : public Pass { log("\n"); log(" -tech greenpak4\n"); log(" map to greenpak4 shift registers.\n"); + log(" this option also implies -clkpol pos -zinit\n"); log("\n"); log(" -tech xilinx\n"); log(" map to xilinx dynamic-length shift registers.\n"); + log(" this option also implies -params -init\n"); log("\n"); } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE |