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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-27 15:29:20 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-27 15:29:20 -0700 |
| commit | a625854ac5e2ff3d6bf11e97b7ac676b362e7461 (patch) | |
| tree | 5a9222a74e058af4fb202f3433aa93ea184b85cf /passes/techmap | |
| parent | 312c03e4ca71f1560a9f47dcd2e9d3de1202179e (diff) | |
| download | yosys-a625854ac5e2ff3d6bf11e97b7ac676b362e7461.tar.gz yosys-a625854ac5e2ff3d6bf11e97b7ac676b362e7461.tar.bz2 yosys-a625854ac5e2ff3d6bf11e97b7ac676b362e7461.zip | |
Do not use Module::remove() iterator version
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/abc9.cc | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index e2a82f0c8..3721b82b7 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -555,17 +555,18 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri dict<IdString, bool> abc_box; vector<RTLIL::Cell*> boxes; - for (auto cell : module->cells()) { + for (const auto &it : module->cells_) { + auto cell = it.second; if (cell->type.in("$_AND_", "$_NOT_")) { module->remove(cell); continue; } - auto it = abc_box.find(cell->type); - if (it == abc_box.end()) { + auto jt = abc_box.find(cell->type); + if (jt == abc_box.end()) { RTLIL::Module* box_module = design->module(cell->type); - it = abc_box.insert(std::make_pair(cell->type, box_module && box_module->attributes.count("\\abc_box_id"))).first; + jt = abc_box.insert(std::make_pair(cell->type, box_module && box_module->attributes.count("\\abc_box_id"))).first; } - if (it->second) + if (jt->second) boxes.emplace_back(cell); } |