aboutsummaryrefslogtreecommitdiffstats
path: root/passes/sat
Commit message (Expand)AuthorAgeFilesLines
* Corrected spelling mistakes found by lintianRuben Undheim2014-09-061-1/+1
* Fixes in old SAT example.ysClifford Wolf2014-09-011-3/+4
* Moved "share" and "wreduce" to passes/opt/Clifford Wolf2014-09-012-988/+0
* azonenberg: Make dump_vcd save model when temporal induction fails due to ste...Clifford Wolf2014-08-241-0/+2
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-151-2/+2
* Fixed "share" for complex scenarios with never-active cellsClifford Wolf2014-08-091-6/+22
* Do not share any $reduce_* cells (its complicated and not worth it anyways)Clifford Wolf2014-08-091-19/+0
* Fixed sharing of reduce operatorClifford Wolf2014-08-081-0/+13
* Added "sat -prove-skip"Clifford Wolf2014-08-081-2/+16
* Use "-keepdc" in "miter -equiv -flatten"Clifford Wolf2014-08-071-2/+2
* Fixed "share" for memory read portsClifford Wolf2014-08-031-0/+7
* Removed at() method from RTLIL::IdStringClifford Wolf2014-08-021-1/+1
* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-021-3/+3
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-024-31/+31
* Renamed modwalker.h to modtools.hClifford Wolf2014-07-311-5/+6
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-314-97/+97
* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-311-1/+1
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-1/+1
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-276-21/+21
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-275-14/+14
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-275-34/+34
* Changed more code to the new RTLIL::Wire constructorsClifford Wolf2014-07-261-42/+13
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-261-18/+5
* More RTLIL::Cell API usage cleanupsClifford Wolf2014-07-261-1/+1
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-261-2/+2
* Manual fixes for new cell connections APIClifford Wolf2014-07-264-12/+21
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-265-116/+116
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-265-116/+116
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-254-65/+20
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-233-13/+5
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-232-10/+4
* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-231-8/+6
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-233-8/+8
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-233-8/+8
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3Clifford Wolf2014-07-231-4/+4
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-221-2/+2
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-226-84/+84
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-226-84/+84
* Removed deprecated module->new_wire()Clifford Wolf2014-07-213-21/+21
* Wider range of cell types supported in "share" passClifford Wolf2014-07-211-17/+197
* Use ezSAT::non_incremental() in "share" passClifford Wolf2014-07-211-0/+2
* Added support for resource sharing in mux control logicClifford Wolf2014-07-201-86/+155
* Supercell creation for $div/$mod worked all along, fixed test benchesClifford Wolf2014-07-201-4/+0
* Fixed creation of shift supercells in "share" passClifford Wolf2014-07-201-4/+20
* Added "miter -equiv -flatten"Clifford Wolf2014-07-201-0/+14
* Added "share" supercell creationClifford Wolf2014-07-201-1/+115
* Added removing of always inactive cells to "share" passClifford Wolf2014-07-201-8/+42
* Progress in "share" passClifford Wolf2014-07-201-112/+185
* Progress in "share" passClifford Wolf2014-07-201-19/+56
* Started to implement real resource sharingClifford Wolf2014-07-192-0/+444