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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 16:11:28 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 16:11:28 +0200 |
| commit | 97a59851a6c411ccb06162d4b31725bf89262378 (patch) | |
| tree | 74cba570ab858657b6fa524cdc9fa45b0493c4be /passes/sat | |
| parent | a84cb0493566f8f5eb610c6d7b67dda85b0f227b (diff) | |
| download | yosys-97a59851a6c411ccb06162d4b31725bf89262378.tar.gz yosys-97a59851a6c411ccb06162d4b31725bf89262378.tar.bz2 yosys-97a59851a6c411ccb06162d4b31725bf89262378.zip | |
Added RTLIL::Cell::has(portname)
Diffstat (limited to 'passes/sat')
| -rw-r--r-- | passes/sat/expose.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index a84faf792..198f83477 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -83,7 +83,7 @@ static void find_dff_wires(std::set<std::string> &dff_wires, RTLIL::Module *modu SigPool dffsignals; for (auto &it : module->cells) { - if (ct.cell_known(it.second->type) && it.second->connections().count("\\Q")) + if (ct.cell_known(it.second->type) && it.second->has("\\Q")) dffsignals.add(sigmap(it.second->get("\\Q"))); } @@ -628,7 +628,7 @@ struct ExposePass : public Pass { log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type)); RTLIL::SigSpec sig; - if (cell->connections().count(p->name) != 0) + if (cell->has(p->name)) sig = cell->connections().at(p->name); sig.extend(w->width); if (w->port_input) |