Use only module->addCell() and module->remove() to create and delete cells

4 files changed, 20 insertions, 65 deletions

diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index c9363f4bf..29ce899ef 100644
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -554,15 +554,12 @@ struct ExposePass : public Pass {
 				if (info.clk_polarity) {
 					module->connections.push_back(RTLIL::SigSig(wire_c, info.sig_clk));
 				} else {
-					RTLIL::Cell *c = new RTLIL::Cell;
-					c->name = NEW_ID;
-					c->type = "$not";
+					RTLIL::Cell *c = module->addCell(NEW_ID, "$not");
 					c->parameters["\\A_SIGNED"] = 0;
 					c->parameters["\\A_WIDTH"] = 1;
 					c->parameters["\\Y_WIDTH"] = 1;
 					c->connections["\\A"] = info.sig_clk;
 					c->connections["\\Y"] = wire_c;
-					module->add(c);
 				}
 
 				if (info.sig_arst != RTLIL::State::Sm)
@@ -575,15 +572,12 @@ struct ExposePass : public Pass {
 					if (info.arst_polarity) {
 						module->connections.push_back(RTLIL::SigSig(wire_r, info.sig_arst));
 					} else {
-						RTLIL::Cell *c = new RTLIL::Cell;
-						c->name = NEW_ID;
-						c->type = "$not";
+						RTLIL::Cell *c = module->addCell(NEW_ID, "$not");
 						c->parameters["\\A_SIGNED"] = 0;
 						c->parameters["\\A_WIDTH"] = 1;
 						c->parameters["\\Y_WIDTH"] = 1;
 						c->connections["\\A"] = info.sig_arst;
 						c->connections["\\Y"] = wire_r;
-						module->add(c);
 					}
 
 					RTLIL::Wire *wire_v = new RTLIL::Wire;
@@ -598,7 +592,7 @@ struct ExposePass : public Pass {
 
 			if (flag_evert)
 			{
-				std::vector<std::string> delete_cells;
+				std::vector<RTLIL::Cell*> delete_cells;
 
 				for (auto &it : module->cells)
 				{
@@ -665,13 +659,12 @@ struct ExposePass : public Pass {
 						}
 					}
 
-					delete_cells.push_back(cell->name);
+					delete_cells.push_back(cell);
 				}
 
-				for (auto &it : delete_cells) {
-					log("Removing cell: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it), RTLIL::id2cstr(module->cells.at(it)->type));
-					delete module->cells.at(it);
-					module->cells.erase(it);
+				for (auto cell : delete_cells) {
+					log("Removing cell: %s/%s (%s)\n", log_id(module), log_id(cell), log_id(cell->type));
+					module->remove(cell);
 				}
 			}
 
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index ba01bc322..79dec3b54 100644
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -718,12 +718,9 @@ struct FreduceWorker
 					{
 						inv_sig = module->addWire(NEW_ID);
 
-						RTLIL::Cell *inv_cell = new RTLIL::Cell;
-						inv_cell->name = NEW_ID;
-						inv_cell->type = "$_INV_";
+						RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_INV_");
 						inv_cell->connections["\\A"] = grp[0].bit;
 						inv_cell->connections["\\Y"] = inv_sig;
-						module->add(inv_cell);
 					}
 
 					module->connections.push_back(RTLIL::SigSig(grp[i].bit, inv_sig));
diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc
index 12384e2cc..aff664242 100644
--- a/passes/sat/miter.cc
+++ b/passes/sat/miter.cc
@@ -115,15 +115,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 	miter_module->name = miter_name;
 	design->modules[miter_name] = miter_module;
 
-	RTLIL::Cell *gold_cell = new RTLIL::Cell;
-	gold_cell->name = "\\gold";
-	gold_cell->type = gold_name;
-	miter_module->add(gold_cell);
-
-	RTLIL::Cell *gate_cell = new RTLIL::Cell;
-	gate_cell->name = "\\gate";
-	gate_cell->type = gate_name;
-	miter_module->add(gate_cell);
+	RTLIL::Cell *gold_cell = miter_module->addCell("\\gold", gold_name);
+	RTLIL::Cell *gate_cell = miter_module->addCell("\\gate", gate_name);
 
 	RTLIL::SigSpec all_conditions;
 
@@ -166,9 +159,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 			{
 				RTLIL::SigSpec gold_x = miter_module->addWire(NEW_ID, w2_gold->width);
 				for (int i = 0; i < w2_gold->width; i++) {
-					RTLIL::Cell *eqx_cell = new RTLIL::Cell;
-					eqx_cell->name = NEW_ID;
-					eqx_cell->type = "$eqx";
+					RTLIL::Cell *eqx_cell = miter_module->addCell(NEW_ID, "$eqx");
 					eqx_cell->parameters["\\A_WIDTH"] = 1;
 					eqx_cell->parameters["\\B_WIDTH"] = 1;
 					eqx_cell->parameters["\\Y_WIDTH"] = 1;
@@ -177,15 +168,12 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 					eqx_cell->connections["\\A"] = RTLIL::SigSpec(w2_gold, i);
 					eqx_cell->connections["\\B"] = RTLIL::State::Sx;
 					eqx_cell->connections["\\Y"] = gold_x.extract(i, 1);
-					miter_module->add(eqx_cell);
 				}
 
 				RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w2_gold->width);
 				RTLIL::SigSpec gate_masked = miter_module->addWire(NEW_ID, w2_gate->width);
 
-				RTLIL::Cell *or_gold_cell = new RTLIL::Cell;
-				or_gold_cell->name = NEW_ID;
-				or_gold_cell->type = "$or";
+				RTLIL::Cell *or_gold_cell = miter_module->addCell(NEW_ID, "$or");
 				or_gold_cell->parameters["\\A_WIDTH"] = w2_gold->width;
 				or_gold_cell->parameters["\\B_WIDTH"] = w2_gold->width;
 				or_gold_cell->parameters["\\Y_WIDTH"] = w2_gold->width;
@@ -194,11 +182,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 				or_gold_cell->connections["\\A"] = w2_gold;
 				or_gold_cell->connections["\\B"] = gold_x;
 				or_gold_cell->connections["\\Y"] = gold_masked;
-				miter_module->add(or_gold_cell);
 
-				RTLIL::Cell *or_gate_cell = new RTLIL::Cell;
-				or_gate_cell->name = NEW_ID;
-				or_gate_cell->type = "$or";
+				RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_ID, "$or");
 				or_gate_cell->parameters["\\A_WIDTH"] = w2_gate->width;
 				or_gate_cell->parameters["\\B_WIDTH"] = w2_gate->width;
 				or_gate_cell->parameters["\\Y_WIDTH"] = w2_gate->width;
@@ -207,11 +192,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 				or_gate_cell->connections["\\A"] = w2_gate;
 				or_gate_cell->connections["\\B"] = gold_x;
 				or_gate_cell->connections["\\Y"] = gate_masked;
-				miter_module->add(or_gate_cell);
 
-				RTLIL::Cell *eq_cell = new RTLIL::Cell;
-				eq_cell->name = NEW_ID;
-				eq_cell->type = "$eqx";
+				RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx");
 				eq_cell->parameters["\\A_WIDTH"] = w2_gold->width;
 				eq_cell->parameters["\\B_WIDTH"] = w2_gate->width;
 				eq_cell->parameters["\\Y_WIDTH"] = 1;
@@ -221,13 +203,10 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 				eq_cell->connections["\\B"] = gate_masked;
 				eq_cell->connections["\\Y"] = miter_module->addWire(NEW_ID);
 				this_condition = eq_cell->connections["\\Y"];
-				miter_module->add(eq_cell);
 			}
 			else
 			{
-				RTLIL::Cell *eq_cell = new RTLIL::Cell;
-				eq_cell->name = NEW_ID;
-				eq_cell->type = "$eqx";
+				RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx");
 				eq_cell->parameters["\\A_WIDTH"] = w2_gold->width;
 				eq_cell->parameters["\\B_WIDTH"] = w2_gate->width;
 				eq_cell->parameters["\\Y_WIDTH"] = 1;
@@ -237,7 +216,6 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 				eq_cell->connections["\\B"] = w2_gate;
 				eq_cell->connections["\\Y"] = miter_module->addWire(NEW_ID);
 				this_condition = eq_cell->connections["\\Y"];
-				miter_module->add(eq_cell);
 			}
 
 			if (flag_make_outcmp)
@@ -254,25 +232,19 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 	}
 
 	if (all_conditions.size() != 1) {
-		RTLIL::Cell *reduce_cell = new RTLIL::Cell;
-		reduce_cell->name = NEW_ID;
-		reduce_cell->type = "$reduce_and";
+		RTLIL::Cell *reduce_cell = miter_module->addCell(NEW_ID, "$reduce_and");
 		reduce_cell->parameters["\\A_WIDTH"] = all_conditions.size();
 		reduce_cell->parameters["\\Y_WIDTH"] = 1;
 		reduce_cell->parameters["\\A_SIGNED"] = 0;
 		reduce_cell->connections["\\A"] = all_conditions;
 		reduce_cell->connections["\\Y"] = miter_module->addWire(NEW_ID);
 		all_conditions = reduce_cell->connections["\\Y"];
-		miter_module->add(reduce_cell);
 	}
 
 	if (flag_make_assert) {
-		RTLIL::Cell *assert_cell = new RTLIL::Cell;
-		assert_cell->name = NEW_ID;
-		assert_cell->type = "$assert";
+		RTLIL::Cell *assert_cell = miter_module->addCell(NEW_ID, "$assert");
 		assert_cell->connections["\\A"] = all_conditions;
 		assert_cell->connections["\\EN"] = RTLIL::SigSpec(1, 1);
-		miter_module->add(assert_cell);
 	}
 
 	RTLIL::Wire *w_trigger = new RTLIL::Wire;
@@ -280,16 +252,13 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 	w_trigger->port_output = true;
 	miter_module->add(w_trigger);
 
-	RTLIL::Cell *not_cell = new RTLIL::Cell;
-	not_cell->name = NEW_ID;
-	not_cell->type = "$not";
+	RTLIL::Cell *not_cell = miter_module->addCell(NEW_ID, "$not");
 	not_cell->parameters["\\A_WIDTH"] = all_conditions.size();
 	not_cell->parameters["\\A_WIDTH"] = all_conditions.size();
 	not_cell->parameters["\\Y_WIDTH"] = w_trigger->width;
 	not_cell->parameters["\\A_SIGNED"] = 0;
 	not_cell->connections["\\A"] = all_conditions;
 	not_cell->connections["\\Y"] = w_trigger;
-	miter_module->add(not_cell);
 
 	miter_module->fixup_ports();
 
diff --git a/passes/sat/share.cc b/passes/sat/share.cc
index ede2fa88c..7e24e1f04 100644
--- a/passes/sat/share.cc
+++ b/passes/sat/share.cc
@@ -282,15 +282,12 @@ struct ShareWorker
 			RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act);
 			RTLIL::Wire *y = module->addWire(NEW_ID, y_width);
 
-			RTLIL::Cell *supercell = new RTLIL::Cell;
-			supercell->name = NEW_ID;
-			supercell->type = c1->type;
+			RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
 			supercell->parameters["\\A_SIGNED"] = a_signed;
 			supercell->parameters["\\A_WIDTH"] = a_width;
 			supercell->parameters["\\Y_WIDTH"] = y_width;
 			supercell->connections["\\A"] = a;
 			supercell->connections["\\Y"] = y;
-			module->add(supercell);
 
 			RTLIL::SigSpec new_y1(y, 0, y1.size());
 			RTLIL::SigSpec new_y2(y, 0, y2.size());
@@ -846,8 +843,7 @@ struct ShareWorker
 			log("Removing %d cells in module %s:\n", SIZE(cells_to_remove), log_id(module));
 			for (auto c : cells_to_remove) {
 				log("  Removing cell %s (%s).\n", log_id(c), log_id(c->type));
-				module->cells.erase(c->name);
-				delete c;
+				module->remove(c);
 			}
 		}