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* Added AIGER witness file co simulationMiodrag Milanovic2022-02-181-1/+93
* simplify logic of handling flip-flops and latchesMiodrag Milanovic2022-02-181-118/+42
* Review cleanupMiodrag Milanovic2022-02-171-6/+5
* Add support for various ff/latch cells simulationMiodrag Milanovic2022-02-161-60/+204
* Merge branch 'master' into clk2ff-better-namesClaire Xen2022-02-1114-88/+534
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| * Merge pull request #3185 from YosysHQ/micko/co_simMiodrag Milanović2022-02-071-21/+430
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| | * Error detection for co-simulationMiodrag Milanovic2022-02-041-0/+3
| | * bug fix and cleanupsMiodrag Milanovic2022-02-041-5/+5
| | * respect hide_internal flagMiodrag Milanovic2022-02-021-1/+1
| | * unify cycles counting and cleanupMiodrag Milanovic2022-02-021-36/+35
| | * added stimulus mode and param checkMiodrag Milanovic2022-02-021-5/+31
| | * error when no signal foundMiodrag Milanovic2022-01-311-0/+2
| | * CleanupMiodrag Milanovic2022-01-311-1/+1
| | * Compare bits when not all are definedMiodrag Milanovic2022-01-311-3/+17
| | * CleanupMiodrag Milanovic2022-01-311-2/+2
| | * message updateMiodrag Milanovic2022-01-311-1/+1
| | * Display simulation time dataMiodrag Milanovic2022-01-311-1/+4
| | * Use edges when explicitMiodrag Milanovic2022-01-311-1/+5
| | * Updating initial state and checksMiodrag Milanovic2022-01-311-15/+28
| | * Fix scopeMiodrag Milanovic2022-01-311-1/+1
| | * check if stop before startMiodrag Milanovic2022-01-281-0/+3
| | * set initial state, only flip-flopsMiodrag Milanovic2022-01-281-1/+28
| | * ignore not found private signalsMiodrag Milanovic2022-01-281-0/+3
| | * recursive checkMiodrag Milanovic2022-01-281-26/+34
| | * Do actual compareMiodrag Milanovic2022-01-281-5/+16
| | * Add more options and time handlingMiodrag Milanovic2022-01-281-2/+103
| | * Display values of outputsMiodrag Milanovic2022-01-261-12/+10
| | * Check if stimulatedMiodrag Milanovic2022-01-261-0/+14
| | * Read fst and use data to set inputsMiodrag Milanovic2022-01-261-10/+92
| | * Add ability to write to FST fileMiodrag Milanovic2022-01-261-11/+109
| * | Add $bmux and $demux cells.Marcelina Kościelnicka2022-01-281-0/+6
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| * FfData: some refactoring.Marcelina Kościelnicka2021-10-072-26/+22
| * kernel/ff: Refactor FfData to enable FFs with async load.Marcelina Kościelnicka2021-10-022-31/+64
| * memory: Introduce $meminit_v2 cell, with EN input.Marcelina Kościelnicka2021-07-281-0/+1
| * Use HTTPS for website links, gatecat emailClaire Xenia Wolf2021-06-091-1/+1
| * Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-0814-15/+15
| * sim: Add wide port support.Marcelina Kościelnicka2021-05-251-3/+3
| * kernel/rtlil: Extract some helpers for checking memory cell types.Marcelina Kościelnicka2021-05-221-1/+1
| * sim: Avoid a crash on empty cell connection.Marcelina Kościelnicka2021-03-081-1/+1
* | clk2fflogic: nice names for autogenerated signalsNoah Moroze2021-03-021-9/+19
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* assertpmux: Fix crash on unused $pmux output.Marcelina Kościelnicka2021-02-221-1/+1
* Add #include needed to build with gcc-11Gabriel Somlo2020-11-261-0/+1
* Add rewrite_filename for sim -vcd argument.Chris Dailey2020-11-241-1/+3
* Merge pull request #2403 from nakengelhardt/sim_timescaleN. Engelhardt2020-10-221-0/+21
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| * use strftime instead of put_time for gcc 4.8 compatibilityN. Engelhardt2020-10-211-4/+5
| * wild guessing at the problem because it builds fine on my machinesN. Engelhardt2020-10-161-0/+3
| * sim -vcd: add date, version, and option for timescaleN. Engelhardt2020-10-161-0/+17
* | sim: Use Mem helper.Marcelina Kościelnicka2020-10-211-103/+90
* | clk2fflogic: Use Mem helper.Marcelina Kościelnicka2020-10-211-68/+45
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* use the new isPublic() in a few placesN. Engelhardt2020-09-142-4/+4
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