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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-01-28 19:41:43 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-01-28 19:41:43 +0100 |
| commit | f04d1398e569d6371a6f31c34ff145096d4a96c9 (patch) | |
| tree | 640d374f0b9f68a875ef5e1ab17fd8e20625c2c2 /passes/sat | |
| parent | ecbba625c4d981ce714434aad51d23a158aabb8a (diff) | |
| download | yosys-f04d1398e569d6371a6f31c34ff145096d4a96c9.tar.gz yosys-f04d1398e569d6371a6f31c34ff145096d4a96c9.tar.bz2 yosys-f04d1398e569d6371a6f31c34ff145096d4a96c9.zip | |
check if stop before start
Diffstat (limited to 'passes/sat')
| -rw-r--r-- | passes/sat/sim.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index d0e0b526c..3cf5967cc 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -1012,6 +1012,9 @@ struct SimWorker : SimShared log_warning("Stop time is after simulation file end time\n"); } } + if (stopCount<startCount) { + log_error("Stop time is before start time\n"); + } auto edges = fst->getAllEdges(fst_clock, startCount, stopCount); fst->reconstructAllAtTimes(edges); bool initial = false; |