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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2022-01-24 16:02:29 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2022-01-28 23:34:41 +0100 |
| commit | 93508d58dafbbffcedffa70b21a197b6fca8bb30 (patch) | |
| tree | 4f4bed22749559a1938457015ff875891fd7a40a /passes/sat | |
| parent | db33b1e535f5ee93dba9ee1cc181b91c482a4dee (diff) | |
| download | yosys-93508d58dafbbffcedffa70b21a197b6fca8bb30.tar.gz yosys-93508d58dafbbffcedffa70b21a197b6fca8bb30.tar.bz2 yosys-93508d58dafbbffcedffa70b21a197b6fca8bb30.zip | |
Add $bmux and $demux cells.
Diffstat (limited to 'passes/sat')
| -rw-r--r-- | passes/sat/sim.cc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 4e158da62..8a44830d2 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -313,6 +313,12 @@ struct SimInstance return; } + // (A,S -> Y) cells + if (has_a && !has_b && !has_c && !has_d && has_s && has_y) { + set_state(sig_y, CellTypes::eval(cell, get_state(sig_a), get_state(sig_s))); + return; + } + // (A,B,S -> Y) cells if (has_a && has_b && !has_c && !has_d && has_s && has_y) { set_state(sig_y, CellTypes::eval(cell, get_state(sig_a), get_state(sig_b), get_state(sig_s))); |