iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	xilinx: xilinx_dsp_cascade to check CREG for DSP48E1 only	Eddie Hung	2020-04-22	1	-1/+1
*	Cleanup use of hard-coded default parameters in light of #1945	Eddie Hung	2020-04-22	7	-48/+48
*	kernel: big fat patch to use more ID::, otherwise ID()	Eddie Hung	2020-04-02	6	-178/+178
*	kernel: use more ID::*	Eddie Hung	2020-04-02	1	-2/+2
*	Merge pull request #1657 from YosysHQ/dave/xilinx-dsp-multonly	David Shah	2020-02-02	1	-0/+7
\|\
\| *	xilinx_dsp: Add multonly scratchpad var to bypass	David Shah	2020-02-01	1	-0/+7
* \|	Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards	Eddie Hung	2020-01-27	1	-1/+1
* \|	ice40: reduce ABC9 internal fanout warnings with a param for CI->I3	Eddie Hung	2020-01-24	1	-3/+12
\|/
*	xilinx_dsp: another typo; move xilinx specific test	Eddie Hung	2020-01-17	1	-1/+1
*	ice40_dsp: fix typo	Eddie Hung	2020-01-17	1	-2/+2
*	Consistency	Eddie Hung	2020-01-17	2	-4/+6
*	xilinx_dsp: add parameter defaults	Eddie Hung	2020-01-17	1	-7/+7
*	ice40_dsp: add default values for parameters	Eddie Hung	2020-01-17	2	-11/+11
*	ice40_dsp: tolerant of fanout-less outputs, as well as all-zero inputs	Eddie Hung	2020-01-17	1	-0/+5
*	fixed invalid char	Miodrag Milanovic	2019-12-25	1	-1/+1
*	Minor nit fixes	Marcin Kościelnicki	2019-12-25	1	-2/+2
*	Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG too	Eddie Hung	2019-12-23	1	-8/+18
*	Fix CEA/CEB check	Eddie Hung	2019-12-23	1	-2/+2
*	Fix checking CE[AB] and for direct connections	Eddie Hung	2019-12-23	1	-18/+40
*	Support unregistered cascades for A and B inputs	Eddie Hung	2019-12-23	1	-47/+74
*	Add DSP48A* PCOUT -> PCIN cascade support	Eddie Hung	2019-12-23	1	-10/+10
*	xilinx_dsp: Initial DSP48A/DSP48A1 support.	Marcin Kościelnicki	2019-12-22	4	-11/+886
*	ice40_wrapcarry -unwrap to preserve 'src' attribute	Eddie Hung	2019-12-09	1	-1/+9
*	-unwrap to create $lut not SB_LUT4 for opt_lut	Eddie Hung	2019-12-09	1	-7/+5
*	Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4	Eddie Hung	2019-12-09	1	-7/+11
*	ice40_wrapcarry to really preserve attributes via -unwrap option	Eddie Hung	2019-12-09	1	-17/+55
*	Drop keep=0 attributes on SB_CARRY	Eddie Hung	2019-12-06	1	-0/+8
*	Merge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPER	Eddie Hung	2019-12-05	1	-0/+1
*	ice40_wrapcarry to preserve SB_CARRY's attributes	Eddie Hung	2019-12-03	1	-0/+2
*	Check for either sign or zero extension for postAdd packing	Eddie Hung	2019-11-26	1	-3/+3
*	Fix #1462, #1480.	Marcin Kościelnicki	2019-11-19	2	-9/+11
*	Makefile: don't assume python is called `python3`	Sean Cross	2019-10-19	1	-2/+2
*	Fix dffmux peepopt init handling	Clifford Wolf	2019-10-16	2	-27/+113
*	Move GENERATE_PATTERN macro to separate utility header	Clifford Wolf	2019-10-16	3	-128/+157
*	Disable left-over log_debug in peepopt_dffmux.pmg	Clifford Wolf	2019-10-16	1	-1/+1
*	Merge pull request #1432 from YosysHQ/eddie/fix1427	Eddie Hung	2019-10-08	1	-47/+81
\|\
\| *	Fix broken CI, check reset even for constants, trim rstmux	Eddie Hung	2019-10-02	1	-23/+26
\| *	Refactor peepopt_dffmux and be sensitive to \init when trimming	Eddie Hung	2019-10-02	1	-32/+63
* \|	Merge pull request #1438 from YosysHQ/eddie/xilinx_dsp_comments	Eddie Hung	2019-10-08	4	-68/+356
\|\ \
\| * \|	Missed this	Eddie Hung	2019-10-05	1	-3/+4
\| * \|	Add comment on why we have to match for clock-enable/reset muxes	Eddie Hung	2019-10-05	3	-3/+11
\| * \|	Add note on pattern detector	Eddie Hung	2019-10-05	1	-3/+7
\| * \|	Add comments for xilinx_dsp_cascade	Eddie Hung	2019-10-04	1	-12/+100
\| * \|	Improve comments for xilinx_dsp_CREG	Eddie Hung	2019-10-04	1	-6/+7
\| * \|	Fix comment	Eddie Hung	2019-10-04	1	-1/+1
\| * \|	Restore optimisation for sigM.empty()	Eddie Hung	2019-10-04	1	-1/+4
\| * \|	Retry on fixing TODOs	Eddie Hung	2019-10-04	2	-13/+1
\| * \|	Revert "Fix TODOs"	Eddie Hung	2019-10-04	2	-0/+20
\| * \|	More comments, cleanup	Eddie Hung	2019-10-04	2	-41/+108
\| * \|	Fix TODOs	Eddie Hung	2019-10-04	2	-20/+0