kernel: big fat patch to use more ID::*, otherwise ID(*)

6 files changed, 178 insertions, 178 deletions

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index c364cd91a..bfddfd0eb 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -73,11 +73,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
 	// SB_MAC16 Input Interface
 	SigSpec A = st.sigA;
-	A.extend_u0(16, st.mul->parameters.at(ID(A_SIGNED), State::S0).as_bool());
+	A.extend_u0(16, st.mul->parameters.at(ID::A_SIGNED, State::S0).as_bool());
 	log_assert(GetSize(A) == 16);
 
 	SigSpec B = st.sigB;
-	B.extend_u0(16, st.mul->parameters.at(ID(B_SIGNED), State::S0).as_bool());
+	B.extend_u0(16, st.mul->parameters.at(ID::B_SIGNED, State::S0).as_bool());
 	log_assert(GetSize(B) == 16);
 
 	SigSpec CD = st.sigCD;
@@ -88,8 +88,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
 	cell->setPort(ID::A, A);
 	cell->setPort(ID::B, B);
-	cell->setPort(ID(C), CD.extract(16, 16));
-	cell->setPort(ID(D), CD.extract(0, 16));
+	cell->setPort(ID::C, CD.extract(16, 16));
+	cell->setPort(ID::D, CD.extract(0, 16));
 
 	cell->setParam(ID(A_REG), st.ffA ? State::S1 : State::S0);
 	cell->setParam(ID(B_REG), st.ffB ? State::S1 : State::S0);
@@ -98,15 +98,15 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
 	SigSpec AHOLD, BHOLD, CDHOLD;
 	if (st.ffAholdmux)
-		AHOLD = st.ffAholdpol ? st.ffAholdmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffAholdmux->getPort(ID(S)));
+		AHOLD = st.ffAholdpol ? st.ffAholdmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffAholdmux->getPort(ID::S));
 	else
 		AHOLD = State::S0;
 	if (st.ffBholdmux)
-		BHOLD = st.ffBholdpol ? st.ffBholdmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffBholdmux->getPort(ID(S)));
+		BHOLD = st.ffBholdpol ? st.ffBholdmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffBholdmux->getPort(ID::S));
 	else
 		BHOLD = State::S0;
 	if (st.ffCDholdmux)
-		CDHOLD = st.ffCDholdpol ? st.ffCDholdmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffCDholdmux->getPort(ID(S)));
+		CDHOLD = st.ffCDholdpol ? st.ffCDholdmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffCDholdmux->getPort(ID::S));
 	else
 		CDHOLD = State::S0;
 	cell->setPort(ID(AHOLD), AHOLD);
@@ -116,11 +116,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
 	SigSpec IRSTTOP, IRSTBOT;
 	if (st.ffArstmux)
-		IRSTTOP = st.ffArstpol ? st.ffArstmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffArstmux->getPort(ID(S)));
+		IRSTTOP = st.ffArstpol ? st.ffArstmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffArstmux->getPort(ID::S));
 	else
 		IRSTTOP = State::S0;
 	if (st.ffBrstmux)
-		IRSTBOT = st.ffBrstpol ? st.ffBrstmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffBrstmux->getPort(ID(S)));
+		IRSTBOT = st.ffBrstpol ? st.ffBrstmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffBrstmux->getPort(ID::S));
 	else
 		IRSTBOT = State::S0;
 	cell->setPort(ID(IRSTTOP), IRSTTOP);
@@ -128,7 +128,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
 	if (st.clock != SigBit())
 	{
-		cell->setPort(ID(CLK), st.clock);
+		cell->setPort(ID::CLK, st.clock);
 		cell->setPort(ID(CE), State::S1);
 		cell->setParam(ID(NEG_TRIGGER), st.clock_pol ? State::S0 : State::S1);
 
@@ -156,7 +156,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	}
 	else
 	{
-		cell->setPort(ID(CLK), State::S0);
+		cell->setPort(ID::CLK, State::S0);
 		cell->setPort(ID(CE), State::S0);
 		cell->setParam(ID(NEG_TRIGGER), State::S0);
 	}
@@ -166,7 +166,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	cell->setPort(ID(SIGNEXTIN), State::Sx);
 	cell->setPort(ID(SIGNEXTOUT), pm.module->addWire(NEW_ID));
 
-	cell->setPort(ID(CI), State::Sx);
+	cell->setPort(ID::CI, State::Sx);
 
 	cell->setPort(ID(ACCUMCI), State::Sx);
 	cell->setPort(ID(ACCUMCO), pm.module->addWire(NEW_ID));
@@ -178,19 +178,19 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	if (O_width == 33) {
 		log_assert(st.add);
 		// If we have a signed multiply-add, then perform sign extension
-		if (st.add->getParam(ID(A_SIGNED)).as_bool() && st.add->getParam(ID(B_SIGNED)).as_bool())
+		if (st.add->getParam(ID::A_SIGNED).as_bool() && st.add->getParam(ID::B_SIGNED).as_bool())
 			pm.module->connect(O[32], O[31]);
 		else
-			cell->setPort(ID(CO), O[32]);
+			cell->setPort(ID::CO, O[32]);
 		O.remove(O_width-1);
 	}
 	else
-		cell->setPort(ID(CO), pm.module->addWire(NEW_ID));
+		cell->setPort(ID::CO, pm.module->addWire(NEW_ID));
 	log_assert(GetSize(O) <= 32);
 	if (GetSize(O) < 32)
 		O.append(pm.module->addWire(NEW_ID, 32-GetSize(O)));
 
-	cell->setPort(ID(O), O);
+	cell->setPort(ID::O, O);
 
 	bool accum = false;
 	if (st.add) {
@@ -208,7 +208,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
 	SigSpec OHOLD;
 	if (st.ffOholdmux)
-		OHOLD = st.ffOholdpol ? st.ffOholdmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffOholdmux->getPort(ID(S)));
+		OHOLD = st.ffOholdpol ? st.ffOholdmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffOholdmux->getPort(ID::S));
 	else
 		OHOLD = State::S0;
 	cell->setPort(ID(OHOLDTOP), OHOLD);
@@ -216,7 +216,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
 	SigSpec ORST;
 	if (st.ffOrstmux)
-		ORST = st.ffOrstpol ? st.ffOrstmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffOrstmux->getPort(ID(S)));
+		ORST = st.ffOrstpol ? st.ffOrstmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffOrstmux->getPort(ID::S));
 	else
 		ORST = State::S0;
 	cell->setPort(ID(ORSTTOP), ORST);
@@ -225,9 +225,9 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	SigSpec acc_reset = State::S0;
 	if (st.mux) {
 		if (st.muxAB == ID::A)
-			acc_reset = st.mux->getPort(ID(S));
+			acc_reset = st.mux->getPort(ID::S);
 		else
-			acc_reset = pm.module->Not(NEW_ID, st.mux->getPort(ID(S)));
+			acc_reset = pm.module->Not(NEW_ID, st.mux->getPort(ID::S));
 	}
 	cell->setPort(ID(OLOADTOP), acc_reset);
 	cell->setPort(ID(OLOADBOT), acc_reset);
@@ -248,8 +248,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	cell->setParam(ID(BOTADDSUB_CARRYSELECT), Const(0, 2));
 
 	cell->setParam(ID(MODE_8x8), State::S0);
-	cell->setParam(ID(A_SIGNED), st.mul->parameters.at(ID(A_SIGNED), State::S0).as_bool());
-	cell->setParam(ID(B_SIGNED), st.mul->parameters.at(ID(B_SIGNED), State::S0).as_bool());
+	cell->setParam(ID::A_SIGNED, st.mul->parameters.at(ID::A_SIGNED, State::S0).as_bool());
+	cell->setParam(ID::B_SIGNED, st.mul->parameters.at(ID::B_SIGNED, State::S0).as_bool());
 
 	if (st.ffO) {
 		if (st.o_lo)
@@ -257,7 +257,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 		else
 			cell->setParam(ID(TOPOUTPUT_SELECT), Const(1, 2));
 
-		st.ffO->connections_.at(ID(Q)).replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
+		st.ffO->connections_.at(ID::Q).replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
 		cell->setParam(ID(BOTOUTPUT_SELECT), Const(1, 2));
 	}
 	else {
diff --git a/passes/pmgen/ice40_wrapcarry.cc b/passes/pmgen/ice40_wrapcarry.cc
index ebe6f62d5..97d2008c2 100644
--- a/passes/pmgen/ice40_wrapcarry.cc
+++ b/passes/pmgen/ice40_wrapcarry.cc
@@ -37,26 +37,26 @@ void create_ice40_wrapcarry(ice40_wrapcarry_pm &pm)
 
 	log("  replacing SB_LUT + SB_CARRY with $__ICE40_CARRY_WRAPPER cell.\n");
 
-	Cell *cell = pm.module->addCell(NEW_ID, "$__ICE40_CARRY_WRAPPER");
+	Cell *cell = pm.module->addCell(NEW_ID, ID($__ICE40_CARRY_WRAPPER));
 	pm.module->swap_names(cell, st.carry);
 
-	cell->setPort(ID::A, st.carry->getPort("\\I0"));
-	cell->setPort(ID::B, st.carry->getPort("\\I1"));
-	auto CI = st.carry->getPort("\\CI");
-	cell->setPort("\\CI", CI);
-	cell->setPort("\\CO", st.carry->getPort("\\CO"));
+	cell->setPort(ID::A, st.carry->getPort(ID(I0)));
+	cell->setPort(ID::B, st.carry->getPort(ID(I1)));
+	auto CI = st.carry->getPort(ID::CI);
+	cell->setPort(ID::CI, CI);
+	cell->setPort(ID::CO, st.carry->getPort(ID::CO));
 
-	cell->setPort("\\I0", st.lut->getPort("\\I0"));
-	auto I3 = st.lut->getPort("\\I3");
+	cell->setPort(ID(I0), st.lut->getPort(ID(I0)));
+	auto I3 = st.lut->getPort(ID(I3));
 	if (pm.sigmap(CI) == pm.sigmap(I3)) {
-		cell->setParam("\\I3_IS_CI", State::S1);
+		cell->setParam(ID(I3_IS_CI), State::S1);
 		I3 = State::Sx;
 	}
 	else
-		cell->setParam("\\I3_IS_CI", State::S0);
-	cell->setPort("\\I3", I3);
-	cell->setPort("\\O", st.lut->getPort("\\O"));
-	cell->setParam("\\LUT", st.lut->getParam("\\LUT_INIT"));
+		cell->setParam(ID(I3_IS_CI), State::S0);
+	cell->setPort(ID(I3), I3);
+	cell->setPort(ID::O, st.lut->getPort(ID::O));
+	cell->setParam(ID::LUT, st.lut->getParam(ID(LUT_INIT)));
 
 	for (const auto &a : st.carry->attributes)
 		cell->attributes[stringf("\\SB_CARRY.%s", a.first.c_str())] = a.second;
@@ -117,18 +117,18 @@ struct Ice40WrapCarryPass : public Pass {
 						continue;
 
 					auto carry = module->addCell(NEW_ID, ID(SB_CARRY));
-					carry->setPort(ID(I0), cell->getPort(ID(A)));
-					carry->setPort(ID(I1), cell->getPort(ID(B)));
-					carry->setPort(ID(CI), cell->getPort(ID(CI)));
-					carry->setPort(ID(CO), cell->getPort(ID(CO)));
+					carry->setPort(ID(I0), cell->getPort(ID::A));
+					carry->setPort(ID(I1), cell->getPort(ID::B));
+					carry->setPort(ID::CI, cell->getPort(ID::CI));
+					carry->setPort(ID::CO, cell->getPort(ID::CO));
 					module->swap_names(carry, cell);
 					auto lut_name = cell->attributes.at(ID(SB_LUT4.name), Const(NEW_ID.str())).decode_string();
 					auto lut = module->addCell(lut_name, ID($lut));
-					lut->setParam(ID(WIDTH), 4);
-					lut->setParam(ID(LUT), cell->getParam(ID(LUT)));
-					auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3));
-					lut->setPort(ID(A), { I3, cell->getPort(ID(B)), cell->getPort(ID(A)), cell->getPort(ID(I0)) });
-					lut->setPort(ID(Y), cell->getPort(ID(O)));
+					lut->setParam(ID::WIDTH, 4);
+					lut->setParam(ID::LUT, cell->getParam(ID::LUT));
+					auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3));
+					lut->setPort(ID::A, { I3, cell->getPort(ID::B), cell->getPort(ID::A), cell->getPort(ID(I0)) });
+					lut->setPort(ID::Y, cell->getPort(ID::O));
 
 					Const src;
 					for (const auto &a : cell->attributes)
@@ -136,16 +136,16 @@ struct Ice40WrapCarryPass : public Pass {
 							carry->attributes[a.first.c_str() + strlen("\\SB_CARRY.")] = a.second;
 						else if (a.first.begins_with("\\SB_LUT4.\\"))
 							lut->attributes[a.first.c_str() + strlen("\\SB_LUT4.")] = a.second;
-						else if (a.first == ID(src))
+						else if (a.first == ID::src)
 							src = a.second;
-						else if (a.first.in(ID(SB_LUT4.name), ID::keep, ID(module_not_derived)))
+						else if (a.first.in(ID(SB_LUT4.name), ID::keep, ID::module_not_derived))
 							continue;
 						else
 							log_abort();
 
 					if (!src.empty()) {
-						carry->attributes.insert(std::make_pair(ID(src), src));
-						lut->attributes.insert(std::make_pair(ID(src), src));
+						carry->attributes.insert(std::make_pair(ID::src, src));
+						lut->attributes.insert(std::make_pair(ID::src, src));
 					}
 
 					module->remove(cell);
diff --git a/passes/pmgen/peepopt.cc b/passes/pmgen/peepopt.cc
index 2230145df..4379ce1e6 100644
--- a/passes/pmgen/peepopt.cc
+++ b/passes/pmgen/peepopt.cc
@@ -87,7 +87,7 @@ struct PeepoptPass : public Pass {
 				peepopt_pm pm(module);
 
 				for (auto w : module->wires()) {
-					auto it = w->attributes.find(ID(init));
+					auto it = w->attributes.find(ID::init);
 					if (it != w->attributes.end()) {
 						SigSpec sig = pm.sigmap(w);
 						Const val = it->second;
@@ -109,7 +109,7 @@ struct PeepoptPass : public Pass {
 				pm.run_dffmux();
 
 				for (auto w : module->wires()) {
-					auto it = w->attributes.find(ID(init));
+					auto it = w->attributes.find(ID::init);
 					if (it != w->attributes.end()) {
 						SigSpec sig = pm.sigmap(w);
 						Const &val = it->second;
diff --git a/passes/pmgen/test_pmgen.cc b/passes/pmgen/test_pmgen.cc
index 72dc18dcc..9cfad03ef 100644
--- a/passes/pmgen/test_pmgen.cc
+++ b/passes/pmgen/test_pmgen.cc
@@ -40,16 +40,16 @@ void reduce_chain(test_pmgen_pm &pm)
 	log("Found chain of length %d (%s):\n", GetSize(ud.longest_chain), log_id(st.first->type));
 
 	SigSpec A;
-	SigSpec Y = ud.longest_chain.front().first->getPort(ID(Y));
+	SigSpec Y = ud.longest_chain.front().first->getPort(ID::Y);
 	auto last_cell = ud.longest_chain.back().first;
 
 	for (auto it : ud.longest_chain) {
 		auto cell = it.first;
 		if (cell == last_cell) {
-			A.append(cell->getPort(ID(A)));
-			A.append(cell->getPort(ID(B)));
+			A.append(cell->getPort(ID::A));
+			A.append(cell->getPort(ID::B));
 		} else {
-			A.append(cell->getPort(it.second == ID(A) ? ID(B) : ID(A)));
+			A.append(cell->getPort(it.second == ID::A ? ID::B : ID::A));
 		}
 		log("    %s\n", log_id(cell));
 		pm.autoremove(cell);
@@ -78,7 +78,7 @@ void reduce_tree(test_pmgen_pm &pm)
 		return;
 
 	SigSpec A = ud.leaves;
-	SigSpec Y = st.first->getPort(ID(Y));
+	SigSpec Y = st.first->getPort(ID::Y);
 	pm.autoremove(st.first);
 
 	log("Found %s tree with %d leaves for %s (%s).\n", log_id(st.first->type),
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index ae7967d7c..f1f4b4206 100644
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -52,7 +52,7 @@ static Cell* addDsp(Module *module) {
 	cell->setParam(ID(USE_SIMD), Const("ONE48"));
 	cell->setParam(ID(USE_DPORT), Const("FALSE"));
 
-	cell->setPort(ID(D), Const(0, 25));
+	cell->setPort(ID::D, Const(0, 25));
 	cell->setPort(ID(INMODE), Const(0, 5));
 	cell->setPort(ID(ALUMODE), Const(0, 4));
 	cell->setPort(ID(OPMODE), Const(0, 7));
@@ -72,15 +72,15 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
 	for (auto cell : selected_cells) {
 		if (!cell->type.in(ID($add), ID($sub)))
 			continue;
-		SigSpec Y = cell->getPort(ID(Y));
+		SigSpec Y = cell->getPort(ID::Y);
 		if (!Y.is_chunk())
 			continue;
 		if (!Y.as_chunk().wire->get_strpool_attribute(ID(use_dsp)).count("simd"))
 			continue;
 		if (GetSize(Y) > 25)
 			continue;
-		SigSpec A = cell->getPort(ID(A));
-		SigSpec B = cell->getPort(ID(B));
+		SigSpec A = cell->getPort(ID::A);
+		SigSpec B = cell->getPort(ID::B);
 		if (GetSize(Y) <= 13) {
 			if (GetSize(A) > 12)
 				continue;
@@ -106,11 +106,11 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
 	}
 
 	auto f12 = [module](SigSpec &AB, SigSpec &C, SigSpec &P, SigSpec &CARRYOUT, Cell *lane) {
-		SigSpec A = lane->getPort(ID(A));
-		SigSpec B = lane->getPort(ID(B));
-		SigSpec Y = lane->getPort(ID(Y));
-		A.extend_u0(12, lane->getParam(ID(A_SIGNED)).as_bool());
-		B.extend_u0(12, lane->getParam(ID(B_SIGNED)).as_bool());
+		SigSpec A = lane->getPort(ID::A);
+		SigSpec B = lane->getPort(ID::B);
+		SigSpec Y = lane->getPort(ID::Y);
+		A.extend_u0(12, lane->getParam(ID::A_SIGNED).as_bool());
+		B.extend_u0(12, lane->getParam(ID::B_SIGNED).as_bool());
 		AB.append(A);
 		C.append(B);
 		if (GetSize(Y) < 13)
@@ -174,10 +174,10 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
 			log_assert(GetSize(C) == 48);
 			log_assert(GetSize(P) == 48);
 			log_assert(GetSize(CARRYOUT) == 4);
-			cell->setPort(ID(A), AB.extract(18, 30));
-			cell->setPort(ID(B), AB.extract(0, 18));
-			cell->setPort(ID(C), C);
-			cell->setPort(ID(P), P);
+			cell->setPort(ID::A, AB.extract(18, 30));
+			cell->setPort(ID::B, AB.extract(0, 18));
+			cell->setPort(ID::C, C);
+			cell->setPort(ID::P, P);
 			cell->setPort(ID(CARRYOUT), CARRYOUT);
 			if (lane1->type == ID($sub))
 				cell->setPort(ID(ALUMODE), Const::from_string("0011"));
@@ -194,11 +194,11 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
 	g12(simd12_sub);
 
 	auto f24 = [module](SigSpec &AB, SigSpec &C, SigSpec &P, SigSpec &CARRYOUT, Cell *lane) {
-		SigSpec A = lane->getPort(ID(A));
-		SigSpec B = lane->getPort(ID(B));
-		SigSpec Y = lane->getPort(ID(Y));
-		A.extend_u0(24, lane->getParam(ID(A_SIGNED)).as_bool());
-		B.extend_u0(24, lane->getParam(ID(B_SIGNED)).as_bool());
+		SigSpec A = lane->getPort(ID::A);
+		SigSpec B = lane->getPort(ID::B);
+		SigSpec Y = lane->getPort(ID::Y);
+		A.extend_u0(24, lane->getParam(ID::A_SIGNED).as_bool());
+		B.extend_u0(24, lane->getParam(ID::B_SIGNED).as_bool());
 		C.append(A);
 		AB.append(B);
 		if (GetSize(Y) < 25)
@@ -238,10 +238,10 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
 			log_assert(GetSize(C) == 48);
 			log_assert(GetSize(P) == 48);
 			log_assert(GetSize(CARRYOUT) == 4);
-			cell->setPort(ID(A), AB.extract(18, 30));
-			cell->setPort(ID(B), AB.extract(0, 18));
-			cell->setPort(ID(C), C);
-			cell->setPort(ID(P), P);
+			cell->setPort(ID::A, AB.extract(18, 30));
+			cell->setPort(ID::B, AB.extract(0, 18));
+			cell->setPort(ID::C, C);
+			cell->setPort(ID::P, P);
 			cell->setPort(ID(CARRYOUT), CARRYOUT);
 			if (lane1->type == ID($sub))
 				cell->setPort(ID(ALUMODE), Const::from_string("0011"));
@@ -280,19 +280,19 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
 
 	if (st.preAdd) {
 		log("  preadder %s (%s)\n", log_id(st.preAdd), log_id(st.preAdd->type));
-		bool A_SIGNED = st.preAdd->getParam(ID(A_SIGNED)).as_bool();
-		bool D_SIGNED = st.preAdd->getParam(ID(B_SIGNED)).as_bool();
-		if (st.sigA == st.preAdd->getPort(ID(B)))
+		bool A_SIGNED = st.preAdd->getParam(ID::A_SIGNED).as_bool();
+		bool D_SIGNED = st.preAdd->getParam(ID::B_SIGNED).as_bool();
+		if (st.sigA == st.preAdd->getPort(ID::B))
 			std::swap(A_SIGNED, D_SIGNED);
 		st.sigA.extend_u0(30, A_SIGNED);
 		st.sigD.extend_u0(25, D_SIGNED);
-		cell->setPort(ID(A), st.sigA);
-		cell->setPort(ID(D), st.sigD);
+		cell->setPort(ID::A, st.sigA);
+		cell->setPort(ID::D, st.sigD);
 		cell->setPort(ID(INMODE), Const::from_string("00100"));
 
 		if (st.ffAD) {
 			if (st.ffADcemux) {
-				SigSpec S = st.ffADcemux->getPort(ID(S));
+				SigSpec S = st.ffADcemux->getPort(ID::S);
 				cell->setPort(ID(CEAD), st.ffADcepol ? S : pm.module->Not(NEW_ID, S));
 			}
 			else
@@ -310,7 +310,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
 		SigSpec &opmode = cell->connections_.at(ID(OPMODE));
 		if (st.postAddMux) {
 			log_assert(st.ffP);
-			opmode[4] = st.postAddMux->getPort(ID(S));
+			opmode[4] = st.postAddMux->getPort(ID::S);
 			pm.autoremove(st.postAddMux);
 		}
 		else if (st.ffP && st.sigC == st.sigP)
@@ -321,11 +321,11 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
 		opmode[5] = State::S1;
 
 		if (opmode[4] != State::S0) {
-			if (st.postAddMuxAB == ID(A))
-				st.sigC.extend_u0(48, st.postAdd->getParam(ID(B_SIGNED)).as_bool());
+			if (st.postAddMuxAB == ID::A)
+				st.sigC.extend_u0(48, st.postAdd->getParam(ID::B_SIGNED).as_bool());
 			else
-				st.sigC.extend_u0(48, st.postAdd->getParam(ID(A_SIGNED)).as_bool());
-			cell->setPort(ID(C), st.sigC);
+				st.sigC.extend_u0(48, st.postAdd->getParam(ID::A_SIGNED).as_bool());
+			cell->setPort(ID::C, st.sigC);
 		}
 
 		pm.autoremove(st.postAdd);
@@ -337,7 +337,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
 		cell->setParam(ID(SEL_MASK), Const("MASK"));
 
 		if (st.overflow->type == ID($ge)) {
-			Const B = st.overflow->getPort(ID(B)).as_const();
+			Const B = st.overflow->getPort(ID::B).as_const();
 			log_assert(std::count(B.bits.begin(), B.bits.end(), State::S1) == 1);
 			// Since B is an exact power of 2, subtract 1
 			//   by inverting all bits up until hitting
@@ -352,7 +352,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
 
 			cell->setParam(ID(MASK), B);
 			cell->setParam(ID(PATTERN), Const(0, 48));
-			cell->setPort(ID(OVERFLOW), st.overflow->getPort(ID(Y)));
+			cell->setPort(ID(OVERFLOW), st.overflow->getPort(ID::Y));
 		}
 		else log_abort();
 
@@ -361,29 +361,29 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
 
 	if (st.clock != SigBit())
 	{
-		cell->setPort(ID(CLK), st.clock);
+		cell->setPort(ID::CLK, st.clock);
 
 		auto f = [&pm,cell](SigSpec &A, Cell* ff, Cell* cemux, bool cepol, IdString ceport, Cell* rstmux, bool rstpol, IdString rstport) {
-			SigSpec D = ff->getPort(ID(D));
-			SigSpec Q = pm.sigmap(ff->getPort(ID(Q)));
+			SigSpec D = ff->getPort(ID::D);
+			SigSpec Q = pm.sigmap(ff->getPort(ID::Q));
 			if (!A.empty())
 				A.replace(Q, D);
 			if (rstmux) {
-				SigSpec Y = rstmux->getPort(ID(Y));
-				SigSpec AB = rstmux->getPort(rstpol ? ID(A) : ID(B));
+				SigSpec Y = rstmux->getPort(ID::Y);
+				SigSpec AB = rstmux->getPort(rstpol ? ID::A : ID::B);
 				if (!A.empty())
 					A.replace(Y, AB);
 				if (rstport != IdString()) {
-					SigSpec S = rstmux->getPort(ID(S));
+					SigSpec S = rstmux->getPort(ID::S);
 					cell->setPort(rstport, rstpol ? S : pm.module->Not(NEW_ID, S));
 				}
 			}
 			else if (rstport != IdString())
 				cell->setPort(rstport, State::S0);
 			if (cemux) {
-				SigSpec Y = cemux->getPort(ID(Y));
-				SigSpec BA = cemux->getPort(cepol ? ID(B) : ID(A));
-				SigSpec S = cemux->getPort(ID(S));
+				SigSpec Y = cemux->getPort(ID::Y);
+				SigSpec BA = cemux->getPort(cepol ? ID::B : ID::A);
+				SigSpec S = cemux->getPort(ID::S);
 				if (!A.empty())
 					A.replace(Y, BA);
 				cell->setPort(ceport, cepol ? S : pm.module->Not(NEW_ID, S));
@@ -392,7 +392,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
 				cell->setPort(ceport, State::S1);
 
 			for (auto c : Q.chunks()) {
-				auto it = c.wire->attributes.find(ID(init));
+				auto it = c.wire->attributes.find(ID::init);
 				if (it == c.wire->attributes.end())
 					continue;
 				for (int i = c.offset; i < c.offset+c.width; i++) {
@@ -403,7 +403,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
 		};
 
 		if (st.ffA2) {
-			SigSpec A = cell->getPort(ID(A));
+			SigSpec A = cell->getPort(ID::A);
 			f(A, st.ffA2, st.ffA2cemux, st.ffA2cepol, ID(CEA2), st.ffA2rstmux, st.ffArstpol, ID(RSTA));
 			if (st.ffA1) {
 				f(A, st.ffA1, st.ffA1cemux, st.ffA1cepol, ID(CEA1), st.ffA1rstmux, st.ffArstpol, IdString());
@@ -415,10 +415,10 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
 				cell->setParam(ID(ACASCREG), 1);
 			}
 			pm.add_siguser(A, cell);
-			cell->setPort(ID(A), A);
+			cell->setPort(ID::A, A);
 		}
 		if (st.ffB2) {
-			SigSpec B = cell->getPort(ID(B));
+			SigSpec B = cell->getPort(ID::B);
 			f(B, st.ffB2, st.ffB2cemux, st.ffB2cepol, ID(CEB2), st.ffB2rstmux, st.ffBrstpol, ID(RSTB));
 			if (st.ffB1) {
 				f(B, st.ffB1, st.ffB1cemux, st.ffB1cepol, ID(CEB1), st.ffB1rstmux, st.ffBrstpol, IdString());
@@ -430,25 +430,25 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
 				cell->setParam(ID(BCASCREG), 1);
 			}
 			pm.add_siguser(B, cell);
-			cell->setPort(ID(B), B);
+			cell->setPort(ID::B, B);
 		}
 		if (st.ffD) {
-			SigSpec D = cell->getPort(ID(D));
+			SigSpec D = cell->getPort(ID::D);
 			f(D, st.ffD, st.ffDcemux, st.ffDcepol, ID(CED), st.ffDrstmux, st.ffDrstpol, ID(RSTD));
 			pm.add_siguser(D, cell);
-			cell->setPort(ID(D), D);
+			cell->setPort(ID::D, D);
 			cell->setParam(ID(DREG), 1);
 		}
 		if (st.ffM) {
 			SigSpec M; // unused
 			f(M, st.ffM, st.ffMcemux, st.ffMcepol, ID(CEM), st.ffMrstmux, st.ffMrstpol, ID(RSTM));
-			st.ffM->connections_.at(ID(Q)).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM)));
+			st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM)));
 			cell->setParam(ID(MREG), State::S1);
 		}
 		if (st.ffP) {
 			SigSpec P; // unused
 			f(P, st.ffP, st.ffPcemux, st.ffPcepol, ID(CEP), st.ffPrstmux, st.ffPrstpol, ID(RSTP));
-			st.ffP->connections_.at(ID(Q)).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP)));
+			st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP)));
 			cell->setParam(ID(PREG), State::S1);
 		}
 
@@ -483,7 +483,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
 	SigSpec P = st.sigP;
 	if (GetSize(P) < 48)
 		P.append(pm.module->addWire(NEW_ID, 48-GetSize(P)));
-	cell->setPort(ID(P), P);
+	cell->setPort(ID::P, P);
 
 	pm.blacklist(cell);
 }
@@ -511,12 +511,12 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
 
 	if (st.preAdd) {
 		log("  preadder %s (%s)\n", log_id(st.preAdd), log_id(st.preAdd->type));
-		bool D_SIGNED = st.preAdd->getParam(ID(A_SIGNED)).as_bool();
-		bool B_SIGNED = st.preAdd->getParam(ID(B_SIGNED)).as_bool();
+		bool D_SIGNED = st.preAdd->getParam(ID::A_SIGNED).as_bool();
+		bool B_SIGNED = st.preAdd->getParam(ID::B_SIGNED).as_bool();
 		st.sigB.extend_u0(18, B_SIGNED);
 		st.sigD.extend_u0(18, D_SIGNED);
-		cell->setPort(ID(B), st.sigB);
-		cell->setPort(ID(D), st.sigD);
+		cell->setPort(ID::B, st.sigB);
+		cell->setPort(ID::D, st.sigD);
 		opmode[4] = State::S1;
 		if (st.preAdd->type == ID($add))
 			opmode[6] = State::S0;
@@ -532,7 +532,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
 
 		if (st.postAddMux) {
 			log_assert(st.ffP);
-			opmode[2] = st.postAddMux->getPort(ID(S));
+			opmode[2] = st.postAddMux->getPort(ID::S);
 			pm.autoremove(st.postAddMux);
 		}
 		else if (st.ffP && st.sigC == st.sigP)
@@ -542,11 +542,11 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
 		opmode[3] = State::S1;
 
 		if (opmode[2] != State::S0) {
-			if (st.postAddMuxAB == ID(A))
-				st.sigC.extend_u0(48, st.postAdd->getParam(ID(B_SIGNED)).as_bool());
+			if (st.postAddMuxAB == ID::A)
+				st.sigC.extend_u0(48, st.postAdd->getParam(ID::B_SIGNED).as_bool());
 			else
-				st.sigC.extend_u0(48, st.postAdd->getParam(ID(A_SIGNED)).as_bool());
-			cell->setPort(ID(C), st.sigC);
+				st.sigC.extend_u0(48, st.postAdd->getParam(ID::A_SIGNED).as_bool());
+			cell->setPort(ID::C, st.sigC);
 		}
 
 		pm.autoremove(st.postAdd);
@@ -554,29 +554,29 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
 
 	if (st.clock != SigBit())
 	{
-		cell->setPort(ID(CLK), st.clock);
+		cell->setPort(ID::CLK, st.clock);
 
 		auto f = [&pm,cell](SigSpec &A, Cell* ff, Cell* cemux, bool cepol, IdString ceport, Cell* rstmux, bool rstpol, IdString rstport) {
-			SigSpec D = ff->getPort(ID(D));
-			SigSpec Q = pm.sigmap(ff->getPort(ID(Q)));
+			SigSpec D = ff->getPort(ID::D);
+			SigSpec Q = pm.sigmap(ff->getPort(ID::Q));
 			if (!A.empty())
 				A.replace(Q, D);
 			if (rstmux) {
-				SigSpec Y = rstmux->getPort(ID(Y));
-				SigSpec AB = rstmux->getPort(rstpol ? ID(A) : ID(B));
+				SigSpec Y = rstmux->getPort(ID::Y);
+				SigSpec AB = rstmux->getPort(rstpol ? ID::A : ID::B);
 				if (!A.empty())
 					A.replace(Y, AB);
 				if (rstport != IdString()) {
-					SigSpec S = rstmux->getPort(ID(S));
+					SigSpec S = rstmux->getPort(ID::S);
 					cell->setPort(rstport, rstpol ? S : pm.module->Not(NEW_ID, S));
 				}
 			}
 			else if (rstport != IdString())
 				cell->setPort(rstport, State::S0);
 			if (cemux) {
-				SigSpec Y = cemux->getPort(ID(Y));
-				SigSpec BA = cemux->getPort(cepol ? ID(B) : ID(A));
-				SigSpec S = cemux->getPort(ID(S));
+				SigSpec Y = cemux->getPort(ID::Y);
+				SigSpec BA = cemux->getPort(cepol ? ID::B : ID::A);
+				SigSpec S = cemux->getPort(ID::S);
 				if (!A.empty())
 					A.replace(Y, BA);
 				cell->setPort(ceport, cepol ? S : pm.module->Not(NEW_ID, S));
@@ -585,7 +585,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
 				cell->setPort(ceport, State::S1);
 
 			for (auto c : Q.chunks()) {
-				auto it = c.wire->attributes.find(ID(init));
+				auto it = c.wire->attributes.find(ID::init);
 				if (it == c.wire->attributes.end())
 					continue;
 				for (int i = c.offset; i < c.offset+c.width; i++) {
@@ -596,7 +596,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
 		};
 
 		if (st.ffA0 || st.ffA1) {
-			SigSpec A = cell->getPort(ID(A));
+			SigSpec A = cell->getPort(ID::A);
 			if (st.ffA1) {
 				f(A, st.ffA1, st.ffA1cemux, st.ffAcepol, ID(CEA), st.ffA1rstmux, st.ffArstpol, ID(RSTA));
 				cell->setParam(ID(A1REG), 1);
@@ -606,10 +606,10 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
 				cell->setParam(ID(A0REG), 1);
 			}
 			pm.add_siguser(A, cell);
-			cell->setPort(ID(A), A);
+			cell->setPort(ID::A, A);
 		}
 		if (st.ffB0 || st.ffB1) {
-			SigSpec B = cell->getPort(ID(B));
+			SigSpec B = cell->getPort(ID::B);
 			if (st.ffB1) {
 				f(B, st.ffB1, st.ffB1cemux, st.ffBcepol, ID(CEB), st.ffB1rstmux, st.ffBrstpol, ID(RSTB));
 				cell->setParam(ID(B1REG), 1);
@@ -619,25 +619,25 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
 				cell->setParam(ID(B0REG), 1);
 			}
 			pm.add_siguser(B, cell);
-			cell->setPort(ID(B), B);
+			cell->setPort(ID::B, B);
 		}
 		if (st.ffD) {
-			SigSpec D = cell->getPort(ID(D));
+			SigSpec D = cell->getPort(ID::D);
 			f(D, st.ffD, st.ffDcemux, st.ffDcepol, ID(CED), st.ffDrstmux, st.ffDrstpol, ID(RSTD));
 			pm.add_siguser(D, cell);
-			cell->setPort(ID(D), D);
+			cell->setPort(ID::D, D);
 			cell->setParam(ID(DREG), 1);
 		}
 		if (st.ffM) {
 			SigSpec M; // unused
 			f(M, st.ffM, st.ffMcemux, st.ffMcepol, ID(CEM), st.ffMrstmux, st.ffMrstpol, ID(RSTM));
-			st.ffM->connections_.at(ID(Q)).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM)));
+			st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM)));
 			cell->setParam(ID(MREG), State::S1);
 		}
 		if (st.ffP) {
 			SigSpec P; // unused
 			f(P, st.ffP, st.ffPcemux, st.ffPcepol, ID(CEP), st.ffPrstmux, st.ffPrstpol, ID(RSTP));
-			st.ffP->connections_.at(ID(Q)).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP)));
+			st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP)));
 			cell->setParam(ID(PREG), State::S1);
 		}
 
@@ -667,7 +667,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
 	SigSpec P = st.sigP;
 	if (GetSize(P) < 48)
 		P.append(pm.module->addWire(NEW_ID, 48-GetSize(P)));
-	cell->setPort(ID(P), P);
+	cell->setPort(ID::P, P);
 
 	pm.blacklist(cell);
 }
@@ -683,29 +683,29 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
 
 	if (st.clock != SigBit())
 	{
-		cell->setPort(ID(CLK), st.clock);
+		cell->setPort(ID::CLK, st.clock);
 
 		auto f = [&pm,cell](SigSpec &A, Cell* ff, Cell* cemux, bool cepol, IdString ceport, Cell* rstmux, bool rstpol, IdString rstport) {
-			SigSpec D = ff->getPort(ID(D));
-			SigSpec Q = pm.sigmap(ff->getPort(ID(Q)));
+			SigSpec D = ff->getPort(ID::D);
+			SigSpec Q = pm.sigmap(ff->getPort(ID::Q));
 			if (!A.empty())
 				A.replace(Q, D);
 			if (rstmux) {
-				SigSpec Y = rstmux->getPort(ID(Y));
-				SigSpec AB = rstmux->getPort(rstpol ? ID(A) : ID(B));
+				SigSpec Y = rstmux->getPort(ID::Y);
+				SigSpec AB = rstmux->getPort(rstpol ? ID::A : ID::B);
 				if (!A.empty())
 					A.replace(Y, AB);
 				if (rstport != IdString()) {
-					SigSpec S = rstmux->getPort(ID(S));
+					SigSpec S = rstmux->getPort(ID::S);
 					cell->setPort(rstport, rstpol ? S : pm.module->Not(NEW_ID, S));
 				}
 			}
 			else if (rstport != IdString())
 				cell->setPort(rstport, State::S0);
 			if (cemux) {
-				SigSpec Y = cemux->getPort(ID(Y));
-				SigSpec BA = cemux->getPort(cepol ? ID(B) : ID(A));
-				SigSpec S = cemux->getPort(ID(S));
+				SigSpec Y = cemux->getPort(ID::Y);
+				SigSpec BA = cemux->getPort(cepol ? ID::B : ID::A);
+				SigSpec S = cemux->getPort(ID::S);
 				if (!A.empty())
 					A.replace(Y, BA);
 				cell->setPort(ceport, cepol ? S : pm.module->Not(NEW_ID, S));
@@ -714,7 +714,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
 				cell->setPort(ceport, State::S1);
 
 			for (auto c : Q.chunks()) {
-				auto it = c.wire->attributes.find(ID(init));
+				auto it = c.wire->attributes.find(ID::init);
 				if (it == c.wire->attributes.end())
 					continue;
 				for (int i = c.offset; i < c.offset+c.width; i++) {
@@ -725,10 +725,10 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
 		};
 
 		if (st.ffC) {
-			SigSpec C = cell->getPort(ID(C));
+			SigSpec C = cell->getPort(ID::C);
 			f(C, st.ffC, st.ffCcemux, st.ffCcepol, ID(CEC), st.ffCrstmux, st.ffCrstpol, ID(RSTC));
 			pm.add_siguser(C, cell);
-			cell->setPort(ID(C), C);
+			cell->setPort(ID::C, C);
 			cell->setParam(ID(CREG), 1);
 		}
 
diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc
index 3d264e8d4..24b525b93 100644
--- a/passes/pmgen/xilinx_srl.cc
+++ b/passes/pmgen/xilinx_srl.cc
@@ -36,9 +36,9 @@ void run_fixed(xilinx_srl_pm &pm)
 	for (auto cell : ud.longest_chain) {
 		log_debug("    %s\n", log_id(cell));
 		if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) {
-			SigBit Q = cell->getPort(ID(Q));
+			SigBit Q = cell->getPort(ID::Q);
 			log_assert(Q.wire);
-			auto it = Q.wire->attributes.find(ID(init));
+			auto it = Q.wire->attributes.find(ID::init);
 			if (it != Q.wire->attributes.end()) {
 				auto &i = it->second[Q.offset];
 				initval.append(i);
@@ -48,7 +48,7 @@ void run_fixed(xilinx_srl_pm &pm)
 				initval.append(State::Sx);
 		}
 		else if (cell->type.in(ID(FDRE), ID(FDRE_1))) {
-			if (cell->parameters.at(ID(INIT), State::S0).as_bool())
+			if (cell->parameters.at(ID::INIT, State::S0).as_bool())
 				initval.append(State::S1);
 			else
 				initval.append(State::S0);
@@ -64,11 +64,11 @@ void run_fixed(xilinx_srl_pm &pm)
 	pm.module->swap_names(c, first_cell);
 
 	if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) {
-		c->setParam(ID(DEPTH), GetSize(ud.longest_chain));
-		c->setParam(ID(INIT), initval.as_const());
+		c->setParam(ID::DEPTH, GetSize(ud.longest_chain));
+		c->setParam(ID::INIT, initval.as_const());
 		if (first_cell->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
 			c->setParam(ID(CLKPOL), 1);
-		else if (first_cell->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1)))
+		else if (first_cell->type.in(ID($_DFF_N_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1)))
 			c->setParam(ID(CLKPOL), 0);
 		else if (first_cell->type.in(ID(FDRE))) {
 			if (!first_cell->parameters.at(ID(IS_C_INVERTED), State::S0).as_bool())
@@ -85,16 +85,16 @@ void run_fixed(xilinx_srl_pm &pm)
 		else
 			c->setParam(ID(ENPOL), 2);
 
-		c->setPort(ID(C), first_cell->getPort(ID(C)));
-		c->setPort(ID(D), first_cell->getPort(ID(D)));
-		c->setPort(ID(Q), last_cell->getPort(ID(Q)));
-		c->setPort(ID(L), GetSize(ud.longest_chain)-1);
+		c->setPort(ID::C, first_cell->getPort(ID::C));
+		c->setPort(ID::D, first_cell->getPort(ID::D));
+		c->setPort(ID::Q, last_cell->getPort(ID::Q));
+		c->setPort(ID::L, GetSize(ud.longest_chain)-1);
 		if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
-			c->setPort(ID(E), State::S1);
+			c->setPort(ID::E, State::S1);
 		else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
-			c->setPort(ID(E), first_cell->getPort(ID(E)));
+			c->setPort(ID::E, first_cell->getPort(ID::E));
 		else if (first_cell->type.in(ID(FDRE), ID(FDRE_1)))
-			c->setPort(ID(E), first_cell->getPort(ID(CE)));
+			c->setPort(ID::E, first_cell->getPort(ID(CE)));
 		else
 			log_abort();
 	}
@@ -117,9 +117,9 @@ void run_variable(xilinx_srl_pm &pm)
 		auto slice = i.second;
 		log_debug("    %s\n", log_id(cell));
 		if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
-			SigBit Q = cell->getPort(ID(Q))[slice];
+			SigBit Q = cell->getPort(ID::Q)[slice];
 			log_assert(Q.wire);
-			auto it = Q.wire->attributes.find(ID(init));
+			auto it = Q.wire->attributes.find(ID::init);
 			if (it != Q.wire->attributes.end()) {
 				auto &i = it->second[Q.offset];
 				initval.append(i);
@@ -140,15 +140,15 @@ void run_variable(xilinx_srl_pm &pm)
 	pm.module->swap_names(c, first_cell);
 
 	if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
-		c->setParam(ID(DEPTH), GetSize(ud.chain));
-		c->setParam(ID(INIT), initval.as_const());
+		c->setParam(ID::DEPTH, GetSize(ud.chain));
+		c->setParam(ID::INIT, initval.as_const());
 		Const clkpol, enpol;
 		if (first_cell->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
 			clkpol = 1;
-		else if (first_cell->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_)))
+		else if (first_cell->type.in(ID($_DFF_N_), ID($_DFFE_NN_), ID($_DFFE_NP_)))
 			clkpol = 0;
 		else if (first_cell->type.in(ID($dff), ID($dffe)))
-			clkpol = first_cell->getParam(ID(CLK_POLARITY));
+			clkpol = first_cell->getParam(ID::CLK_POLARITY);
 		else
 			log_abort();
 		if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
@@ -156,27 +156,27 @@ void run_variable(xilinx_srl_pm &pm)
 		else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_)))
 			enpol = 0;
 		else if (first_cell->type.in(ID($dffe)))
-			enpol = first_cell->getParam(ID(EN_POLARITY));
+			enpol = first_cell->getParam(ID::EN_POLARITY);
 		else
 			enpol = 2;
 		c->setParam(ID(CLKPOL), clkpol);
 		c->setParam(ID(ENPOL), enpol);
 
 		if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
-			c->setPort(ID(C), first_cell->getPort(ID(C)));
+			c->setPort(ID::C, first_cell->getPort(ID::C));
 		else if (first_cell->type.in(ID($dff), ID($dffe)))
-			c->setPort(ID(C), first_cell->getPort(ID(CLK)));
+			c->setPort(ID::C, first_cell->getPort(ID::CLK));
 		else
 			log_abort();
-		c->setPort(ID(D), first_cell->getPort(ID(D))[first_slice]);
-		c->setPort(ID(Q), st.shiftx->getPort(ID(Y)));
-		c->setPort(ID(L), st.shiftx->getPort(ID(B)));
+		c->setPort(ID::D, first_cell->getPort(ID::D)[first_slice]);
+		c->setPort(ID::Q, st.shiftx->getPort(ID::Y));
+		c->setPort(ID::L, st.shiftx->getPort(ID::B));
 		if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($dff)))
-			c->setPort(ID(E), State::S1);
+			c->setPort(ID::E, State::S1);
 		else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
-			c->setPort(ID(E), first_cell->getPort(ID(E)));
+			c->setPort(ID::E, first_cell->getPort(ID::E));
 		else if (first_cell->type.in(ID($dffe)))
-			c->setPort(ID(E), first_cell->getPort(ID(EN)));
+			c->setPort(ID::E, first_cell->getPort(ID::EN));
 		else
 			log_abort();
 	}