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| author | David Shah <dave@ds0.me> | 2020-01-27 11:19:27 +0000 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2020-02-01 15:30:43 +0000 |
| commit | 65716c998272704c057d846076dc3258c74f5a34 (patch) | |
| tree | cbd7b6dee5cc7179d381155429cdef6bf1ce3533 /passes/pmgen | |
| parent | b7be6cfd6544a351b885a869008bf10cec189b8b (diff) | |
| download | yosys-65716c998272704c057d846076dc3258c74f5a34.tar.gz yosys-65716c998272704c057d846076dc3258c74f5a34.tar.bz2 yosys-65716c998272704c057d846076dc3258c74f5a34.zip | |
xilinx_dsp: Add multonly scratchpad var to bypass
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'passes/pmgen')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 81c3c57c4..ae7967d7c 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -767,6 +767,9 @@ struct XilinxDspPass : public Pass { log("to a maximum length of 20 cells, corresponding to the smallest Xilinx 7 Series\n"); log("device.\n"); log("\n"); + log("This pass is a no-op if the scratchpad variable 'xilinx_dsp.multonly' is set\n"); + log("to 1.\n"); + log("\n"); log("\n"); log("Experimental feature: addition/subtractions less than 12 or 24 bits with the\n"); log("'(* use_dsp=\"simd\" *)' attribute attached to the output wire or attached to\n"); @@ -805,6 +808,10 @@ struct XilinxDspPass : public Pass { family = "xcu"; for (auto module : design->selected_modules()) { + + if (design->scratchpad_get_bool("xilinx_dsp.multonly")) + continue; + // Experimental feature: pack $add/$sub cells with // (* use_dsp48="simd" *) into DSP48E1's using its // SIMD feature |