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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-05 08:57:37 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-05 08:57:37 -0700 |
| commit | f90a4b1e24e36943a343bd36315b6029dd6cd044 (patch) | |
| tree | cd4e7e876750704cae91250ba1957a82926192ef /passes/pmgen | |
| parent | 991c2ca95bfac2bedd9fd622dbef15611021a8be (diff) | |
| download | yosys-f90a4b1e24e36943a343bd36315b6029dd6cd044.tar.gz yosys-f90a4b1e24e36943a343bd36315b6029dd6cd044.tar.bz2 yosys-f90a4b1e24e36943a343bd36315b6029dd6cd044.zip | |
Missed this
Diffstat (limited to 'passes/pmgen')
| -rw-r--r-- | passes/pmgen/xilinx_dsp_CREG.pmg | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/passes/pmgen/xilinx_dsp_CREG.pmg b/passes/pmgen/xilinx_dsp_CREG.pmg index 2408d483a..a57043009 100644 --- a/passes/pmgen/xilinx_dsp_CREG.pmg +++ b/passes/pmgen/xilinx_dsp_CREG.pmg @@ -105,9 +105,10 @@ endcode // ####################### // Subpattern for matching against input registers, based on knowledge of the -// 'Q' input. Typically, this task would be handled by other Yosys passes -// such as dff2dffe, but since DSP inference happens much before this, these -// patterns have to be manually identified. +// 'Q' input. Typically, identifying registers with clock-enable and reset +// capability would be a task would be handled by other Yosys passes such as +// dff2dffe, but since DSP inference happens much before this, these patterns +// have to be manually identified. // At a high level: // (1) Starting from a $dff cell that (partially or fully) drives the given // 'Q' argument |