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| author | David Shah <dave@ds0.me> | 2020-02-02 14:53:32 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-02-02 14:53:32 +0000 |
| commit | 1055b6b1dd7e4a557b33f6dc4bb14b09dcd582dc (patch) | |
| tree | 7d1ce26e6d48109f573a5f0e99bb03af42f12bc9 /passes/pmgen | |
| parent | b44d0e041f09216dd90dccd3f18f146b1dfb7e92 (diff) | |
| parent | 65716c998272704c057d846076dc3258c74f5a34 (diff) | |
| download | yosys-1055b6b1dd7e4a557b33f6dc4bb14b09dcd582dc.tar.gz yosys-1055b6b1dd7e4a557b33f6dc4bb14b09dcd582dc.tar.bz2 yosys-1055b6b1dd7e4a557b33f6dc4bb14b09dcd582dc.zip | |
Merge pull request #1657 from YosysHQ/dave/xilinx-dsp-multonly
synth_xilinx: add -dsp-multonly
Diffstat (limited to 'passes/pmgen')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 81c3c57c4..ae7967d7c 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -767,6 +767,9 @@ struct XilinxDspPass : public Pass { log("to a maximum length of 20 cells, corresponding to the smallest Xilinx 7 Series\n"); log("device.\n"); log("\n"); + log("This pass is a no-op if the scratchpad variable 'xilinx_dsp.multonly' is set\n"); + log("to 1.\n"); + log("\n"); log("\n"); log("Experimental feature: addition/subtractions less than 12 or 24 bits with the\n"); log("'(* use_dsp=\"simd\" *)' attribute attached to the output wire or attached to\n"); @@ -805,6 +808,10 @@ struct XilinxDspPass : public Pass { family = "xcu"; for (auto module : design->selected_modules()) { + + if (design->scratchpad_get_bool("xilinx_dsp.multonly")) + continue; + // Experimental feature: pack $add/$sub cells with // (* use_dsp48="simd" *) into DSP48E1's using its // SIMD feature |