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* CleanupEddie Hung2019-08-281-4/+0
* No need to replace Q of slice since $shiftx is autoremove-dEddie Hung2019-08-281-1/+0
* More cleanupEddie Hung2019-08-281-9/+6
* Do not use default_params dict, hardcode default values, cleanupEddie Hung2019-08-281-16/+13
* Missing close bracketEddie Hung2019-08-261-1/+1
* Remove leftover headerEddie Hung2019-08-261-1/+0
* Create new $__XILINX_SHREG_ cell for variable length tooEddie Hung2019-08-231-31/+30
* Create new cell for fixed length SRLEddie Hung2019-08-231-14/+22
* Fix last_cell.DEddie Hung2019-08-231-2/+1
* Update docEddie Hung2019-08-231-12/+19
* Remove (* init *) entry when consumed into SRLEddie Hung2019-08-231-2/+6
* Forgot to sliceEddie Hung2019-08-231-1/+2
* xilinx_srl to use 'slice' features of pmgen for word levelEddie Hung2019-08-231-16/+31
* Add docEddie Hung2019-08-221-1/+14
* Add copyrightEddie Hung2019-08-221-0/+1
* Remove output_bitsEddie Hung2019-08-221-12/+1
* Forgot to set ud_variable.minlenEddie Hung2019-08-221-0/+1
* Do not run xilinx_srl_pm in fixed loopEddie Hung2019-08-221-28/+24
* Add commentEddie Hung2019-08-211-0/+4
* Add variable length support to xilinx_srlEddie Hung2019-08-211-12/+100
* Rename pattern to fixedEddie Hung2019-08-211-9/+9
* xilinx_srl to support FDRE and FDRE_1Eddie Hung2019-08-211-6/+23
* Fix polarity of EN_POLEddie Hung2019-08-211-2/+2
* Add CLKPOL == 0Eddie Hung2019-08-211-0/+2
* Reject if not minlen from inside pattern matcherEddie Hung2019-08-211-7/+9
* Add init supportEddie Hung2019-08-211-2/+11
* Fix spacingEddie Hung2019-08-211-2/+2
* Initial progress on xilinx_srlEddie Hung2019-08-211-0/+115