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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 11:02:17 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 11:02:17 -0700 |
| commit | 231ddbf95cb2541eb73622e7dcb2744b2308f584 (patch) | |
| tree | 25858e80d65966ec8d49da43928db3af160c7119 /passes/pmgen/xilinx_srl.cc | |
| parent | 61639d5387cceec6f6c50b851c4c44d6b4f93dad (diff) | |
| download | yosys-231ddbf95cb2541eb73622e7dcb2744b2308f584.tar.gz yosys-231ddbf95cb2541eb73622e7dcb2744b2308f584.tar.bz2 yosys-231ddbf95cb2541eb73622e7dcb2744b2308f584.zip | |
Forgot to set ud_variable.minlen
Diffstat (limited to 'passes/pmgen/xilinx_srl.cc')
| -rw-r--r-- | passes/pmgen/xilinx_srl.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index 36833839b..d1dbd77ae 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -204,6 +204,7 @@ struct XilinxSrlPass : public Pass { for (auto module : design->selected_modules()) { auto pm = xilinx_srl_pm(module, module->selected_cells()); pm.ud_fixed.minlen = minlen; + pm.ud_variable.minlen = minlen; if (fixed) { // TODO: How to get these automatically? |