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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 12:54:11 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 12:54:11 -0700 |
| commit | df53fe12e7ed667d36d3829681cfc43a3355b834 (patch) | |
| tree | e5881d2b1ecc6d2594c1e23e4eb4683b23c4c4e3 /passes/pmgen/xilinx_srl.cc | |
| parent | 02507124868144145526a39b0718319bf9db12a7 (diff) | |
| download | yosys-df53fe12e7ed667d36d3829681cfc43a3355b834.tar.gz yosys-df53fe12e7ed667d36d3829681cfc43a3355b834.tar.bz2 yosys-df53fe12e7ed667d36d3829681cfc43a3355b834.zip | |
Fix spacing
Diffstat (limited to 'passes/pmgen/xilinx_srl.cc')
| -rw-r--r-- | passes/pmgen/xilinx_srl.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index 2d052534d..bfda55af0 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -93,7 +93,7 @@ struct XilinxSrlPass : public Pass { { log_header(design, "Executing XILINX_SRL pass (Xilinx shift register extraction).\n"); - int minlen = 3; + int minlen = 3; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -106,7 +106,7 @@ struct XilinxSrlPass : public Pass { } extra_args(args, argidx, design); - auto f = std::bind(reduce_chain, std::placeholders::_1, minlen); + auto f = std::bind(reduce_chain, std::placeholders::_1, minlen); for (auto module : design->selected_modules()) while (xilinx_srl_pm(module, module->selected_cells()).run_reduce(f)) {} } |