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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-26 21:02:52 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-26 21:02:52 -0700 |
| commit | 9172d4a6740145e7b3c7c34b8fb5effd23598a94 (patch) | |
| tree | e61d4add9c954763b6df988d5457b444e536e8f1 /passes/pmgen/xilinx_srl.cc | |
| parent | 6b5e65919a6ec14d4bfc85f80d1f7492d5b86c16 (diff) | |
| download | yosys-9172d4a6740145e7b3c7c34b8fb5effd23598a94.tar.gz yosys-9172d4a6740145e7b3c7c34b8fb5effd23598a94.tar.bz2 yosys-9172d4a6740145e7b3c7c34b8fb5effd23598a94.zip | |
Missing close bracket
Diffstat (limited to 'passes/pmgen/xilinx_srl.cc')
| -rw-r--r-- | passes/pmgen/xilinx_srl.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index a8264cab2..b9cdbfaa1 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -213,7 +213,7 @@ struct XilinxSrlPass : public Pass { log("\n"); log(" -variable\n"); log(" infer variable-length shift registers (i.e. fixed-length shifts where\n"); - log(" each element also fans-out to a $shiftx cell.\n"); + log(" each element also fans-out to a $shiftx cell).\n"); log("\n"); } |