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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 13:06:59 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 13:06:59 -0700 |
| commit | 5939ffdc077eb155e5ecf21da08bb18b69924854 (patch) | |
| tree | 43cf0e0f0544a538f369189f0121cbe0faa8b92d /passes/pmgen/xilinx_srl.cc | |
| parent | 242b3083eac817c927624db735ca3196223f97c0 (diff) | |
| download | yosys-5939ffdc077eb155e5ecf21da08bb18b69924854.tar.gz yosys-5939ffdc077eb155e5ecf21da08bb18b69924854.tar.bz2 yosys-5939ffdc077eb155e5ecf21da08bb18b69924854.zip | |
Forgot to slice
Diffstat (limited to 'passes/pmgen/xilinx_srl.cc')
| -rw-r--r-- | passes/pmgen/xilinx_srl.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index da7acf745..e21a826df 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -106,6 +106,7 @@ void run_variable(xilinx_srl_pm &pm) log("Found variable chain of length %d (%s):\n", GetSize(ud.chain), log_id(st.first->type)); auto last_cell = ud.chain.back().first; + auto last_slice = ud.chain.back().second; SigSpec initval; for (const auto &i : ud.chain) { @@ -130,7 +131,7 @@ void run_variable(xilinx_srl_pm &pm) pm.autoremove(st.shiftx); Cell *c = last_cell; - SigBit Q = st.first->getPort(ID(Q)); + SigBit Q = st.first->getPort(ID(Q))[last_slice]; c->setPort(ID(Q), Q); if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) { |