iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Cleanup	Eddie Hung	2019-08-28	1	-4/+0
*	No need to replace Q of slice since $shiftx is autoremove-d	Eddie Hung	2019-08-28	1	-1/+0
*	More cleanup	Eddie Hung	2019-08-28	1	-9/+6
*	Do not use default_params dict, hardcode default values, cleanup	Eddie Hung	2019-08-28	1	-16/+13
*	Missing close bracket	Eddie Hung	2019-08-26	1	-1/+1
*	Remove leftover header	Eddie Hung	2019-08-26	1	-1/+0
*	Create new $__XILINX_SHREG_ cell for variable length too	Eddie Hung	2019-08-23	1	-31/+30
*	Create new cell for fixed length SRL	Eddie Hung	2019-08-23	1	-14/+22
*	Fix last_cell.D	Eddie Hung	2019-08-23	1	-2/+1
*	Update doc	Eddie Hung	2019-08-23	1	-12/+19
*	Remove (* init *) entry when consumed into SRL	Eddie Hung	2019-08-23	1	-2/+6
*	Forgot to slice	Eddie Hung	2019-08-23	1	-1/+2
*	xilinx_srl to use 'slice' features of pmgen for word level	Eddie Hung	2019-08-23	1	-16/+31
*	Add doc	Eddie Hung	2019-08-22	1	-1/+14
*	Add copyright	Eddie Hung	2019-08-22	1	-0/+1
*	Remove output_bits	Eddie Hung	2019-08-22	1	-12/+1
*	Forgot to set ud_variable.minlen	Eddie Hung	2019-08-22	1	-0/+1
*	Do not run xilinx_srl_pm in fixed loop	Eddie Hung	2019-08-22	1	-28/+24
*	Add comment	Eddie Hung	2019-08-21	1	-0/+4
*	Add variable length support to xilinx_srl	Eddie Hung	2019-08-21	1	-12/+100
*	Rename pattern to fixed	Eddie Hung	2019-08-21	1	-9/+9
*	xilinx_srl to support FDRE and FDRE_1	Eddie Hung	2019-08-21	1	-6/+23
*	Fix polarity of EN_POL	Eddie Hung	2019-08-21	1	-2/+2
*	Add CLKPOL == 0	Eddie Hung	2019-08-21	1	-0/+2
*	Reject if not minlen from inside pattern matcher	Eddie Hung	2019-08-21	1	-7/+9
*	Add init support	Eddie Hung	2019-08-21	1	-2/+11
*	Fix spacing	Eddie Hung	2019-08-21	1	-2/+2
*	Initial progress on xilinx_srl	Eddie Hung	2019-08-21	1	-0/+115