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* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
* synth_xilinx: Use opt_dff.Marcelina Koƛcielnicka2020-07-301-88/+71
* Use C++11 final/override keywords.whitequark2020-06-181-2/+2
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-94/+94
* xilinx_dsp: Add multonly scratchpad var to bypassDavid Shah2020-02-011-0/+7
* xilinx_dsp: Initial DSP48A/DSP48A1 support.Marcin Koƛcielnicki2019-12-221-6/+206
* Merge pull request #1438 from YosysHQ/eddie/xilinx_dsp_commentsEddie Hung2019-10-081-3/+11
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| * Fix commentEddie Hung2019-10-041-1/+1
| * Add comments for xilinx_dspEddie Hung2019-10-041-3/+11
* | Fixes for MSVC buildMiodrag Milanovic2019-10-041-0/+1
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* Update doc with max cascade chain of 20Eddie Hung2019-09-261-2/+4
* Do not always zero out C (e.g. during cascade breaks)Eddie Hung2019-09-261-2/+0
* Update docEddie Hung2019-09-261-1/+2
* xilinx_dsp_cascade to also cascade AREG and BREGEddie Hung2019-09-261-23/+19
* Remove newlineEddie Hung2019-09-261-1/+0
* Fix memory issue since SigSpec& could be invalidatedEddie Hung2019-09-251-6/+10
* Set [AB]CASCREG to legal valuesEddie Hung2019-09-231-6/+10
* Comment to explain separating CREG packingEddie Hung2019-09-231-0/+8
* Separate out CREG packing into new pattern, to avoid conflict with PREGEddie Hung2019-09-231-21/+87
* Use new port/param overload in pmgEddie Hung2019-09-201-1/+1
* Output pattern matcher items as log_debug()Eddie Hung2019-09-201-18/+16
* Do not run xilinx_dsp_cascadeAB for nowEddie Hung2019-09-201-1/+2
* Run until convergenceEddie Hung2019-09-201-3/+9
* Add a xilinx_dsp_cascade matcher for PCIN -> PCOUTEddie Hung2019-09-201-52/+8
* ClarifyEddie Hung2019-09-191-1/+2
* Fix width of DEddie Hung2019-09-191-1/+1
* Use ID() macroEddie Hung2019-09-191-136/+136
* Re-enable sign extension for C inputEddie Hung2019-09-191-4/+4
* Add doc on pattern detector for overflowEddie Hung2019-09-181-0/+5
* Check overflow condition is power of 2 without using int32Eddie Hung2019-09-181-3/+13
* Add support for overflow using pattern detectorEddie Hung2019-09-181-0/+19
* Set more ports explicitlyEddie Hung2019-09-121-0/+2
* Add support for A1 and B1 registersEddie Hung2019-09-111-19/+40
* Rename {A,B} -> {A2,B2}Eddie Hung2019-09-111-14/+14
* Add PCOUT -> PCIN non-shifted cascadingEddie Hung2019-09-111-15/+22
* Input registers to add DSP as new siguser to block upstream packingEddie Hung2019-09-111-8/+16
* More cleanupEddie Hung2019-09-111-62/+28
* Add support for A/B/C/D/AD resetEddie Hung2019-09-111-83/+38
* Add support for RSTMEddie Hung2019-09-111-10/+21
* Only pack out registers if \init is zero or x; then remove \init from PREGEddie Hung2019-09-101-0/+10
* Fix RSTPEddie Hung2019-09-101-1/+1
* Add support for RSTPEddie Hung2019-09-101-4/+12
* enpol -> cepolEddie Hung2019-09-101-11/+11
* Update help textEddie Hung2019-09-101-3/+3
* Update xilinx_dsp help textEddie Hung2019-09-101-3/+21
* OopsEddie Hung2019-09-091-0/+1
* Support subtraction as wellEddie Hung2019-09-091-112/+123
* Support TWO24Eddie Hung2019-09-091-1/+59
* RefactorEddie Hung2019-09-091-33/+33
* Add initial USE_SIMD=FOUR12 supportEddie Hung2019-09-091-0/+157