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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-10 20:51:48 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-10 20:51:48 -0700 |
| commit | af147d14300a8fbff2db8d823cf3622ec5a81ca6 (patch) | |
| tree | 74b6b9ae835396085a86c1d30d2075f9a1fa9bda /passes/pmgen/xilinx_dsp.cc | |
| parent | c6df55a9e7c9827a6b971cc885b83fdb69b269d3 (diff) | |
| download | yosys-af147d14300a8fbff2db8d823cf3622ec5a81ca6.tar.gz yosys-af147d14300a8fbff2db8d823cf3622ec5a81ca6.tar.bz2 yosys-af147d14300a8fbff2db8d823cf3622ec5a81ca6.zip | |
Add support for RSTP
Diffstat (limited to 'passes/pmgen/xilinx_dsp.cc')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index a5fa67083..fe82b1307 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -273,7 +273,8 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) log("postAdd: %s\n", log_id(st.postAdd, "--")); log("postAddMux: %s\n", log_id(st.postAddMux, "--")); log("ffP: %s\n", log_id(st.ffP, "--")); - log("ffPmux: %s\n", log_id(st.ffPmux, "--")); + log("ffPcemux: %s\n", log_id(st.ffPcemux, "--")); + log("ffPrstmux: %s\n", log_id(st.ffPrstmux, "--")); #endif log("Analysing %s.%s for Xilinx DSP packing.\n", log_id(pm.module), log_id(st.dsp)); @@ -431,10 +432,17 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) pm.autoremove(st.ffM); } if (st.ffP) { - if (st.ffPmux) { - SigSpec S = st.ffPmux->getPort("\\S"); + if (st.ffPrstmux) { + SigSpec S = st.ffPrstmux->getPort("\\S"); + cell->setPort("\\RSTP", st.ffPrstpol ? S : pm.module->Not(NEW_ID, S)); + st.ffPrstmux->connections_.at("\\Y").replace(P, pm.module->addWire(NEW_ID, GetSize(P))); + } + else + cell->setPort("\\RSTP", State::S1); + if (st.ffPcemux) { + SigSpec S = st.ffPcemux->getPort("\\S"); cell->setPort("\\CEP", st.ffPcepol ? S : pm.module->Not(NEW_ID, S)); - st.ffPmux->connections_.at("\\Y").replace(P, pm.module->addWire(NEW_ID, GetSize(P))); + st.ffPcemux->connections_.at("\\Y").replace(P, pm.module->addWire(NEW_ID, GetSize(P))); } else cell->setPort("\\CEP", State::S1); |