kernel: big fat patch to use more ID::*, otherwise ID(*)

1 files changed, 94 insertions, 94 deletions

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index ae7967d7c..f1f4b4206 100644
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -52,7 +52,7 @@ static Cell* addDsp(Module *module) {
 	cell->setParam(ID(USE_SIMD), Const("ONE48"));
 	cell->setParam(ID(USE_DPORT), Const("FALSE"));
 
-	cell->setPort(ID(D), Const(0, 25));
+	cell->setPort(ID::D, Const(0, 25));
 	cell->setPort(ID(INMODE), Const(0, 5));
 	cell->setPort(ID(ALUMODE), Const(0, 4));
 	cell->setPort(ID(OPMODE), Const(0, 7));
@@ -72,15 +72,15 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
 	for (auto cell : selected_cells) {
 		if (!cell->type.in(ID($add), ID($sub)))
 			continue;
-		SigSpec Y = cell->getPort(ID(Y));
+		SigSpec Y = cell->getPort(ID::Y);
 		if (!Y.is_chunk())
 			continue;
 		if (!Y.as_chunk().wire->get_strpool_attribute(ID(use_dsp)).count("simd"))
 			continue;
 		if (GetSize(Y) > 25)
 			continue;
-		SigSpec A = cell->getPort(ID(A));
-		SigSpec B = cell->getPort(ID(B));
+		SigSpec A = cell->getPort(ID::A);
+		SigSpec B = cell->getPort(ID::B);
 		if (GetSize(Y) <= 13) {
 			if (GetSize(A) > 12)
 				continue;
@@ -106,11 +106,11 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
 	}
 
 	auto f12 = [module](SigSpec &AB, SigSpec &C, SigSpec &P, SigSpec &CARRYOUT, Cell *lane) {
-		SigSpec A = lane->getPort(ID(A));
-		SigSpec B = lane->getPort(ID(B));
-		SigSpec Y = lane->getPort(ID(Y));
-		A.extend_u0(12, lane->getParam(ID(A_SIGNED)).as_bool());
-		B.extend_u0(12, lane->getParam(ID(B_SIGNED)).as_bool());
+		SigSpec A = lane->getPort(ID::A);
+		SigSpec B = lane->getPort(ID::B);
+		SigSpec Y = lane->getPort(ID::Y);
+		A.extend_u0(12, lane->getParam(ID::A_SIGNED).as_bool());
+		B.extend_u0(12, lane->getParam(ID::B_SIGNED).as_bool());
 		AB.append(A);
 		C.append(B);
 		if (GetSize(Y) < 13)
@@ -174,10 +174,10 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
 			log_assert(GetSize(C) == 48);
 			log_assert(GetSize(P) == 48);
 			log_assert(GetSize(CARRYOUT) == 4);
-			cell->setPort(ID(A), AB.extract(18, 30));
-			cell->setPort(ID(B), AB.extract(0, 18));
-			cell->setPort(ID(C), C);
-			cell->setPort(ID(P), P);
+			cell->setPort(ID::A, AB.extract(18, 30));
+			cell->setPort(ID::B, AB.extract(0, 18));
+			cell->setPort(ID::C, C);
+			cell->setPort(ID::P, P);
 			cell->setPort(ID(CARRYOUT), CARRYOUT);
 			if (lane1->type == ID($sub))
 				cell->setPort(ID(ALUMODE), Const::from_string("0011"));
@@ -194,11 +194,11 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
 	g12(simd12_sub);
 
 	auto f24 = [module](SigSpec &AB, SigSpec &C, SigSpec &P, SigSpec &CARRYOUT, Cell *lane) {
-		SigSpec A = lane->getPort(ID(A));
-		SigSpec B = lane->getPort(ID(B));
-		SigSpec Y = lane->getPort(ID(Y));
-		A.extend_u0(24, lane->getParam(ID(A_SIGNED)).as_bool());
-		B.extend_u0(24, lane->getParam(ID(B_SIGNED)).as_bool());
+		SigSpec A = lane->getPort(ID::A);
+		SigSpec B = lane->getPort(ID::B);
+		SigSpec Y = lane->getPort(ID::Y);
+		A.extend_u0(24, lane->getParam(ID::A_SIGNED).as_bool());
+		B.extend_u0(24, lane->getParam(ID::B_SIGNED).as_bool());
 		C.append(A);
 		AB.append(B);
 		if (GetSize(Y) < 25)
@@ -238,10 +238,10 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
 			log_assert(GetSize(C) == 48);
 			log_assert(GetSize(P) == 48);
 			log_assert(GetSize(CARRYOUT) == 4);
-			cell->setPort(ID(A), AB.extract(18, 30));
-			cell->setPort(ID(B), AB.extract(0, 18));
-			cell->setPort(ID(C), C);
-			cell->setPort(ID(P), P);
+			cell->setPort(ID::A, AB.extract(18, 30));
+			cell->setPort(ID::B, AB.extract(0, 18));
+			cell->setPort(ID::C, C);
+			cell->setPort(ID::P, P);
 			cell->setPort(ID(CARRYOUT), CARRYOUT);
 			if (lane1->type == ID($sub))
 				cell->setPort(ID(ALUMODE), Const::from_string("0011"));
@@ -280,19 +280,19 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
 
 	if (st.preAdd) {
 		log("  preadder %s (%s)\n", log_id(st.preAdd), log_id(st.preAdd->type));
-		bool A_SIGNED = st.preAdd->getParam(ID(A_SIGNED)).as_bool();
-		bool D_SIGNED = st.preAdd->getParam(ID(B_SIGNED)).as_bool();
-		if (st.sigA == st.preAdd->getPort(ID(B)))
+		bool A_SIGNED = st.preAdd->getParam(ID::A_SIGNED).as_bool();
+		bool D_SIGNED = st.preAdd->getParam(ID::B_SIGNED).as_bool();
+		if (st.sigA == st.preAdd->getPort(ID::B))
 			std::swap(A_SIGNED, D_SIGNED);
 		st.sigA.extend_u0(30, A_SIGNED);
 		st.sigD.extend_u0(25, D_SIGNED);
-		cell->setPort(ID(A), st.sigA);
-		cell->setPort(ID(D), st.sigD);
+		cell->setPort(ID::A, st.sigA);
+		cell->setPort(ID::D, st.sigD);
 		cell->setPort(ID(INMODE), Const::from_string("00100"));
 
 		if (st.ffAD) {
 			if (st.ffADcemux) {
-				SigSpec S = st.ffADcemux->getPort(ID(S));
+				SigSpec S = st.ffADcemux->getPort(ID::S);
 				cell->setPort(ID(CEAD), st.ffADcepol ? S : pm.module->Not(NEW_ID, S));
 			}
 			else
@@ -310,7 +310,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
 		SigSpec &opmode = cell->connections_.at(ID(OPMODE));
 		if (st.postAddMux) {
 			log_assert(st.ffP);
-			opmode[4] = st.postAddMux->getPort(ID(S));
+			opmode[4] = st.postAddMux->getPort(ID::S);
 			pm.autoremove(st.postAddMux);
 		}
 		else if (st.ffP && st.sigC == st.sigP)
@@ -321,11 +321,11 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
 		opmode[5] = State::S1;
 
 		if (opmode[4] != State::S0) {
-			if (st.postAddMuxAB == ID(A))
-				st.sigC.extend_u0(48, st.postAdd->getParam(ID(B_SIGNED)).as_bool());
+			if (st.postAddMuxAB == ID::A)
+				st.sigC.extend_u0(48, st.postAdd->getParam(ID::B_SIGNED).as_bool());
 			else
-				st.sigC.extend_u0(48, st.postAdd->getParam(ID(A_SIGNED)).as_bool());
-			cell->setPort(ID(C), st.sigC);
+				st.sigC.extend_u0(48, st.postAdd->getParam(ID::A_SIGNED).as_bool());
+			cell->setPort(ID::C, st.sigC);
 		}
 
 		pm.autoremove(st.postAdd);
@@ -337,7 +337,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
 		cell->setParam(ID(SEL_MASK), Const("MASK"));
 
 		if (st.overflow->type == ID($ge)) {
-			Const B = st.overflow->getPort(ID(B)).as_const();
+			Const B = st.overflow->getPort(ID::B).as_const();
 			log_assert(std::count(B.bits.begin(), B.bits.end(), State::S1) == 1);
 			// Since B is an exact power of 2, subtract 1
 			//   by inverting all bits up until hitting
@@ -352,7 +352,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
 
 			cell->setParam(ID(MASK), B);
 			cell->setParam(ID(PATTERN), Const(0, 48));
-			cell->setPort(ID(OVERFLOW), st.overflow->getPort(ID(Y)));
+			cell->setPort(ID(OVERFLOW), st.overflow->getPort(ID::Y));
 		}
 		else log_abort();
 
@@ -361,29 +361,29 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
 
 	if (st.clock != SigBit())
 	{
-		cell->setPort(ID(CLK), st.clock);
+		cell->setPort(ID::CLK, st.clock);
 
 		auto f = [&pm,cell](SigSpec &A, Cell* ff, Cell* cemux, bool cepol, IdString ceport, Cell* rstmux, bool rstpol, IdString rstport) {
-			SigSpec D = ff->getPort(ID(D));
-			SigSpec Q = pm.sigmap(ff->getPort(ID(Q)));
+			SigSpec D = ff->getPort(ID::D);
+			SigSpec Q = pm.sigmap(ff->getPort(ID::Q));
 			if (!A.empty())
 				A.replace(Q, D);
 			if (rstmux) {
-				SigSpec Y = rstmux->getPort(ID(Y));
-				SigSpec AB = rstmux->getPort(rstpol ? ID(A) : ID(B));
+				SigSpec Y = rstmux->getPort(ID::Y);
+				SigSpec AB = rstmux->getPort(rstpol ? ID::A : ID::B);
 				if (!A.empty())
 					A.replace(Y, AB);
 				if (rstport != IdString()) {
-					SigSpec S = rstmux->getPort(ID(S));
+					SigSpec S = rstmux->getPort(ID::S);
 					cell->setPort(rstport, rstpol ? S : pm.module->Not(NEW_ID, S));
 				}
 			}
 			else if (rstport != IdString())
 				cell->setPort(rstport, State::S0);
 			if (cemux) {
-				SigSpec Y = cemux->getPort(ID(Y));
-				SigSpec BA = cemux->getPort(cepol ? ID(B) : ID(A));
-				SigSpec S = cemux->getPort(ID(S));
+				SigSpec Y = cemux->getPort(ID::Y);
+				SigSpec BA = cemux->getPort(cepol ? ID::B : ID::A);
+				SigSpec S = cemux->getPort(ID::S);
 				if (!A.empty())
 					A.replace(Y, BA);
 				cell->setPort(ceport, cepol ? S : pm.module->Not(NEW_ID, S));
@@ -392,7 +392,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
 				cell->setPort(ceport, State::S1);
 
 			for (auto c : Q.chunks()) {
-				auto it = c.wire->attributes.find(ID(init));
+				auto it = c.wire->attributes.find(ID::init);
 				if (it == c.wire->attributes.end())
 					continue;
 				for (int i = c.offset; i < c.offset+c.width; i++) {
@@ -403,7 +403,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
 		};
 
 		if (st.ffA2) {
-			SigSpec A = cell->getPort(ID(A));
+			SigSpec A = cell->getPort(ID::A);
 			f(A, st.ffA2, st.ffA2cemux, st.ffA2cepol, ID(CEA2), st.ffA2rstmux, st.ffArstpol, ID(RSTA));
 			if (st.ffA1) {
 				f(A, st.ffA1, st.ffA1cemux, st.ffA1cepol, ID(CEA1), st.ffA1rstmux, st.ffArstpol, IdString());
@@ -415,10 +415,10 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
 				cell->setParam(ID(ACASCREG), 1);
 			}
 			pm.add_siguser(A, cell);
-			cell->setPort(ID(A), A);
+			cell->setPort(ID::A, A);
 		}
 		if (st.ffB2) {
-			SigSpec B = cell->getPort(ID(B));
+			SigSpec B = cell->getPort(ID::B);
 			f(B, st.ffB2, st.ffB2cemux, st.ffB2cepol, ID(CEB2), st.ffB2rstmux, st.ffBrstpol, ID(RSTB));
 			if (st.ffB1) {
 				f(B, st.ffB1, st.ffB1cemux, st.ffB1cepol, ID(CEB1), st.ffB1rstmux, st.ffBrstpol, IdString());
@@ -430,25 +430,25 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
 				cell->setParam(ID(BCASCREG), 1);
 			}
 			pm.add_siguser(B, cell);
-			cell->setPort(ID(B), B);
+			cell->setPort(ID::B, B);
 		}
 		if (st.ffD) {
-			SigSpec D = cell->getPort(ID(D));
+			SigSpec D = cell->getPort(ID::D);
 			f(D, st.ffD, st.ffDcemux, st.ffDcepol, ID(CED), st.ffDrstmux, st.ffDrstpol, ID(RSTD));
 			pm.add_siguser(D, cell);
-			cell->setPort(ID(D), D);
+			cell->setPort(ID::D, D);
 			cell->setParam(ID(DREG), 1);
 		}
 		if (st.ffM) {
 			SigSpec M; // unused
 			f(M, st.ffM, st.ffMcemux, st.ffMcepol, ID(CEM), st.ffMrstmux, st.ffMrstpol, ID(RSTM));
-			st.ffM->connections_.at(ID(Q)).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM)));
+			st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM)));
 			cell->setParam(ID(MREG), State::S1);
 		}
 		if (st.ffP) {
 			SigSpec P; // unused
 			f(P, st.ffP, st.ffPcemux, st.ffPcepol, ID(CEP), st.ffPrstmux, st.ffPrstpol, ID(RSTP));
-			st.ffP->connections_.at(ID(Q)).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP)));
+			st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP)));
 			cell->setParam(ID(PREG), State::S1);
 		}
 
@@ -483,7 +483,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
 	SigSpec P = st.sigP;
 	if (GetSize(P) < 48)
 		P.append(pm.module->addWire(NEW_ID, 48-GetSize(P)));
-	cell->setPort(ID(P), P);
+	cell->setPort(ID::P, P);
 
 	pm.blacklist(cell);
 }
@@ -511,12 +511,12 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
 
 	if (st.preAdd) {
 		log("  preadder %s (%s)\n", log_id(st.preAdd), log_id(st.preAdd->type));
-		bool D_SIGNED = st.preAdd->getParam(ID(A_SIGNED)).as_bool();
-		bool B_SIGNED = st.preAdd->getParam(ID(B_SIGNED)).as_bool();
+		bool D_SIGNED = st.preAdd->getParam(ID::A_SIGNED).as_bool();
+		bool B_SIGNED = st.preAdd->getParam(ID::B_SIGNED).as_bool();
 		st.sigB.extend_u0(18, B_SIGNED);
 		st.sigD.extend_u0(18, D_SIGNED);
-		cell->setPort(ID(B), st.sigB);
-		cell->setPort(ID(D), st.sigD);
+		cell->setPort(ID::B, st.sigB);
+		cell->setPort(ID::D, st.sigD);
 		opmode[4] = State::S1;
 		if (st.preAdd->type == ID($add))
 			opmode[6] = State::S0;
@@ -532,7 +532,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
 
 		if (st.postAddMux) {
 			log_assert(st.ffP);
-			opmode[2] = st.postAddMux->getPort(ID(S));
+			opmode[2] = st.postAddMux->getPort(ID::S);
 			pm.autoremove(st.postAddMux);
 		}
 		else if (st.ffP && st.sigC == st.sigP)
@@ -542,11 +542,11 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
 		opmode[3] = State::S1;
 
 		if (opmode[2] != State::S0) {
-			if (st.postAddMuxAB == ID(A))
-				st.sigC.extend_u0(48, st.postAdd->getParam(ID(B_SIGNED)).as_bool());
+			if (st.postAddMuxAB == ID::A)
+				st.sigC.extend_u0(48, st.postAdd->getParam(ID::B_SIGNED).as_bool());
 			else
-				st.sigC.extend_u0(48, st.postAdd->getParam(ID(A_SIGNED)).as_bool());
-			cell->setPort(ID(C), st.sigC);
+				st.sigC.extend_u0(48, st.postAdd->getParam(ID::A_SIGNED).as_bool());
+			cell->setPort(ID::C, st.sigC);
 		}
 
 		pm.autoremove(st.postAdd);
@@ -554,29 +554,29 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
 
 	if (st.clock != SigBit())
 	{
-		cell->setPort(ID(CLK), st.clock);
+		cell->setPort(ID::CLK, st.clock);
 
 		auto f = [&pm,cell](SigSpec &A, Cell* ff, Cell* cemux, bool cepol, IdString ceport, Cell* rstmux, bool rstpol, IdString rstport) {
-			SigSpec D = ff->getPort(ID(D));
-			SigSpec Q = pm.sigmap(ff->getPort(ID(Q)));
+			SigSpec D = ff->getPort(ID::D);
+			SigSpec Q = pm.sigmap(ff->getPort(ID::Q));
 			if (!A.empty())
 				A.replace(Q, D);
 			if (rstmux) {
-				SigSpec Y = rstmux->getPort(ID(Y));
-				SigSpec AB = rstmux->getPort(rstpol ? ID(A) : ID(B));
+				SigSpec Y = rstmux->getPort(ID::Y);
+				SigSpec AB = rstmux->getPort(rstpol ? ID::A : ID::B);
 				if (!A.empty())
 					A.replace(Y, AB);
 				if (rstport != IdString()) {
-					SigSpec S = rstmux->getPort(ID(S));
+					SigSpec S = rstmux->getPort(ID::S);
 					cell->setPort(rstport, rstpol ? S : pm.module->Not(NEW_ID, S));
 				}
 			}
 			else if (rstport != IdString())
 				cell->setPort(rstport, State::S0);
 			if (cemux) {
-				SigSpec Y = cemux->getPort(ID(Y));
-				SigSpec BA = cemux->getPort(cepol ? ID(B) : ID(A));
-				SigSpec S = cemux->getPort(ID(S));
+				SigSpec Y = cemux->getPort(ID::Y);
+				SigSpec BA = cemux->getPort(cepol ? ID::B : ID::A);
+				SigSpec S = cemux->getPort(ID::S);
 				if (!A.empty())
 					A.replace(Y, BA);
 				cell->setPort(ceport, cepol ? S : pm.module->Not(NEW_ID, S));
@@ -585,7 +585,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
 				cell->setPort(ceport, State::S1);
 
 			for (auto c : Q.chunks()) {
-				auto it = c.wire->attributes.find(ID(init));
+				auto it = c.wire->attributes.find(ID::init);
 				if (it == c.wire->attributes.end())
 					continue;
 				for (int i = c.offset; i < c.offset+c.width; i++) {
@@ -596,7 +596,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
 		};
 
 		if (st.ffA0 || st.ffA1) {
-			SigSpec A = cell->getPort(ID(A));
+			SigSpec A = cell->getPort(ID::A);
 			if (st.ffA1) {
 				f(A, st.ffA1, st.ffA1cemux, st.ffAcepol, ID(CEA), st.ffA1rstmux, st.ffArstpol, ID(RSTA));
 				cell->setParam(ID(A1REG), 1);
@@ -606,10 +606,10 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
 				cell->setParam(ID(A0REG), 1);
 			}
 			pm.add_siguser(A, cell);
-			cell->setPort(ID(A), A);
+			cell->setPort(ID::A, A);
 		}
 		if (st.ffB0 || st.ffB1) {
-			SigSpec B = cell->getPort(ID(B));
+			SigSpec B = cell->getPort(ID::B);
 			if (st.ffB1) {
 				f(B, st.ffB1, st.ffB1cemux, st.ffBcepol, ID(CEB), st.ffB1rstmux, st.ffBrstpol, ID(RSTB));
 				cell->setParam(ID(B1REG), 1);
@@ -619,25 +619,25 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
 				cell->setParam(ID(B0REG), 1);
 			}
 			pm.add_siguser(B, cell);
-			cell->setPort(ID(B), B);
+			cell->setPort(ID::B, B);
 		}
 		if (st.ffD) {
-			SigSpec D = cell->getPort(ID(D));
+			SigSpec D = cell->getPort(ID::D);
 			f(D, st.ffD, st.ffDcemux, st.ffDcepol, ID(CED), st.ffDrstmux, st.ffDrstpol, ID(RSTD));
 			pm.add_siguser(D, cell);
-			cell->setPort(ID(D), D);
+			cell->setPort(ID::D, D);
 			cell->setParam(ID(DREG), 1);
 		}
 		if (st.ffM) {
 			SigSpec M; // unused
 			f(M, st.ffM, st.ffMcemux, st.ffMcepol, ID(CEM), st.ffMrstmux, st.ffMrstpol, ID(RSTM));
-			st.ffM->connections_.at(ID(Q)).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM)));
+			st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM)));
 			cell->setParam(ID(MREG), State::S1);
 		}
 		if (st.ffP) {
 			SigSpec P; // unused
 			f(P, st.ffP, st.ffPcemux, st.ffPcepol, ID(CEP), st.ffPrstmux, st.ffPrstpol, ID(RSTP));
-			st.ffP->connections_.at(ID(Q)).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP)));
+			st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP)));
 			cell->setParam(ID(PREG), State::S1);
 		}
 
@@ -667,7 +667,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
 	SigSpec P = st.sigP;
 	if (GetSize(P) < 48)
 		P.append(pm.module->addWire(NEW_ID, 48-GetSize(P)));
-	cell->setPort(ID(P), P);
+	cell->setPort(ID::P, P);
 
 	pm.blacklist(cell);
 }
@@ -683,29 +683,29 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
 
 	if (st.clock != SigBit())
 	{
-		cell->setPort(ID(CLK), st.clock);
+		cell->setPort(ID::CLK, st.clock);
 
 		auto f = [&pm,cell](SigSpec &A, Cell* ff, Cell* cemux, bool cepol, IdString ceport, Cell* rstmux, bool rstpol, IdString rstport) {
-			SigSpec D = ff->getPort(ID(D));
-			SigSpec Q = pm.sigmap(ff->getPort(ID(Q)));
+			SigSpec D = ff->getPort(ID::D);
+			SigSpec Q = pm.sigmap(ff->getPort(ID::Q));
 			if (!A.empty())
 				A.replace(Q, D);
 			if (rstmux) {
-				SigSpec Y = rstmux->getPort(ID(Y));
-				SigSpec AB = rstmux->getPort(rstpol ? ID(A) : ID(B));
+				SigSpec Y = rstmux->getPort(ID::Y);
+				SigSpec AB = rstmux->getPort(rstpol ? ID::A : ID::B);
 				if (!A.empty())
 					A.replace(Y, AB);
 				if (rstport != IdString()) {
-					SigSpec S = rstmux->getPort(ID(S));
+					SigSpec S = rstmux->getPort(ID::S);
 					cell->setPort(rstport, rstpol ? S : pm.module->Not(NEW_ID, S));
 				}
 			}
 			else if (rstport != IdString())
 				cell->setPort(rstport, State::S0);
 			if (cemux) {
-				SigSpec Y = cemux->getPort(ID(Y));
-				SigSpec BA = cemux->getPort(cepol ? ID(B) : ID(A));
-				SigSpec S = cemux->getPort(ID(S));
+				SigSpec Y = cemux->getPort(ID::Y);
+				SigSpec BA = cemux->getPort(cepol ? ID::B : ID::A);
+				SigSpec S = cemux->getPort(ID::S);
 				if (!A.empty())
 					A.replace(Y, BA);
 				cell->setPort(ceport, cepol ? S : pm.module->Not(NEW_ID, S));
@@ -714,7 +714,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
 				cell->setPort(ceport, State::S1);
 
 			for (auto c : Q.chunks()) {
-				auto it = c.wire->attributes.find(ID(init));
+				auto it = c.wire->attributes.find(ID::init);
 				if (it == c.wire->attributes.end())
 					continue;
 				for (int i = c.offset; i < c.offset+c.width; i++) {
@@ -725,10 +725,10 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
 		};
 
 		if (st.ffC) {
-			SigSpec C = cell->getPort(ID(C));
+			SigSpec C = cell->getPort(ID::C);
 			f(C, st.ffC, st.ffCcemux, st.ffCcepol, ID(CEC), st.ffCrstmux, st.ffCrstpol, ID(RSTC));
 			pm.add_siguser(C, cell);
-			cell->setPort(ID(C), C);
+			cell->setPort(ID::C, C);
 			cell->setParam(ID(CREG), 1);
 		}