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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-26 13:44:41 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-26 13:44:41 -0700 |
| commit | 95f0dd57df5209f77df6771e381b87871ab9860a (patch) | |
| tree | faf5c7b056e8605ba0e0c3d707878ad7d1727dda /passes/pmgen/xilinx_dsp.cc | |
| parent | 58f31096abbb0bc68c8339c88b7db410b8edcdba (diff) | |
| download | yosys-95f0dd57df5209f77df6771e381b87871ab9860a.tar.gz yosys-95f0dd57df5209f77df6771e381b87871ab9860a.tar.bz2 yosys-95f0dd57df5209f77df6771e381b87871ab9860a.zip | |
Update doc
Diffstat (limited to 'passes/pmgen/xilinx_dsp.cc')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index b0251de50..5ccc47ba8 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -578,7 +578,8 @@ struct XilinxDspPass : public Pass { log("Use of the dedicated 'PCOUT' -> 'PCIN' cascade path is detected for 'P' -> 'C'\n"); log("connections (optionally, where 'P' is right-shifted by 17-bits and used as an\n"); log("input to the post-adder -- a pattern common for summing partial products to\n"); - log("implement wide multipliers).\n"); + log("implement wide multipliers). Initial support also exists for similar cascading\n"); + log("for AREG and BREG using '[AB]OUT' -> '[AB]IN'.\n"); log("\n"); log("\n"); log("Experimental feature: addition/subtractions less than 12 or 24 bits with the\n"); |