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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-20 14:21:22 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-20 14:21:22 -0700 |
| commit | 53817b85753deb3dc5647414de67de1373798049 (patch) | |
| tree | 7d46afa0000187b7fccbe1a446f8cb6593921aee /passes/pmgen/xilinx_dsp.cc | |
| parent | d122083a112d51ba0d91e44c37b1d4d9d11080aa (diff) | |
| download | yosys-53817b85753deb3dc5647414de67de1373798049.tar.gz yosys-53817b85753deb3dc5647414de67de1373798049.tar.bz2 yosys-53817b85753deb3dc5647414de67de1373798049.zip | |
Use new port/param overload in pmg
Diffstat (limited to 'passes/pmgen/xilinx_dsp.cc')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 1612b66ec..9d0a77e2b 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -290,7 +290,7 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm) st.sigD.extend_u0(25, D_SIGNED); cell->setPort(ID(A), st.sigA); cell->setPort(ID(D), st.sigD); - cell->connections_.at(ID(INMODE)) = Const::from_string("00100"); + cell->setPort(ID(INMODE), Const::from_string("00100")); if (st.ffAD) { if (st.ffADcemux) { |